MCM67A618FN10 datasheet, PDF - EEWORLD Datasheet

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MCM67A618FN10: Description64K x 18 Bit Asychronous/Latched Address Fast Static RAM; Categorystorage storage; File Size106KB，12 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM67A618FN10 Overview

64K x 18 Bit Asychronous/Latched Address Fast Static RAM

MCM67A618FN10 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
package instruction	PLASTIC, LCC-52
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	10 ns
Other features	BYTE WRITE
I/O type	COMMON
JESD-30 code	S-PQCC-J52
JESD-609 code	e0
length	19.1262 mm
memory density	1179648 bi
Memory IC Type	CACHE TAG SRAM
memory width	18
Number of functions	1
Number of ports	1
Number of terminals	52
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX18
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum standby current	0.02 A
Minimum standby current	4.75 V
Maximum slew rate	0.29 mA
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	BICMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	19.1262 mm

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM67A618/D

64K x 18 Bit Asynchronous/

Latched Address Fast Static RAM

The MCM67A618 is a 1,179,648 bit latched address static random access

memory organized as 65,536 words of 18 bits, fabricated with Motorola’s high–

performance silicon–gate BiCMOS technology. The device integrates a 64K x 18

SRAM core with advanced peripheral circuitry consisting of address and data in-

put latches, active low chip enable, separate upper and lower byte write strobes,

and a fast output enable. This device has increased output drive capability sup-

ported by multiple power pins.

Address, data in, and chip enable latches are provided. When latch enables

(AL for address and chip enables and DL for data in) are high, the address, data

in, and chip enable latches are in the transparent state. If latch enables are tied

high the device can be used as an asynchronous SRAM. When latch enables are

low the address, data in, and chip enable latches are in the latched state. This

input latch simplifies read and write cycles by guaranteeing address and data–in

hold time in a simple fashion.

Dual write enables (LW and UW) are provided to allow individually writeable

bytes. LW controls DQ0 – DQ8 (the lower bits) while UW controls DQ9 – DQ17

(the upper bits).

Six pair of power and ground pins have been utilized and placed on the pack-

age for maximum performance.

The MCM67A618 will be available in a 52–pin plastic leaded chip carrier

(PLCC).

This device is ideally suited for systems that require wide data bus widths,

cache memory, and tag RAMs.

•

Single 5 V

5% Power Supply

Fast Access Times: 10/12/15 ns Max

Byte Writeable via Dual Write Enables

Separate Data Input Latch for Simplified Write Cycles

Address and Chip Enable Input Latches

Common Data Inputs and Data Outputs

Output Enable Controlled Three–State Outputs

3.3 V I/O Compatible

High Board Density 52–Lead PLCC Package

MCM67A618

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENT

VCC

V SS

A10

DQ9

DQ10

VCC

VSS

DQ11

DQ12

DQ13

DQ14

VSS

VCC

DQ15

DQ16

DQ17

3 2 1 52 51 50 49 48 47

20 21 22 23 24 25 26 27 28 29 30 31 32 33

V SS

V CC

A15

A14

A13

A12

A11

7 6 5 4

DQ8

DQ7

DQ6

VCC

VSS

DQ5

DQ4

DQ3

DQ2

VSS

VCC

DQ1

DQ0

PIN NAMES

A0 – A15 . . . . . . . . . . . . . . . . Address Inputs

AL . . . . . . . . . . . . . . . . . . . . . . Address Latch

DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch

LW . . . . . . . . . . . . Lower Byte Write Enable

UW . . . . . . . . . . . . Higher Byte Write Enable

E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 – DQ17 . . . . . . . . . . . Data Input/Output

VCC . . . . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

All power supply and ground pins must be con-

nected for proper operation of the device.

REV 4

5/95

Motorola, Inc. 1994

MOTOROLA FAST SRAM

MCM67A618

MCM67A618FN10 Related Products

	MCM67A618FN10	MCM67A618FN15	MCM67A618FN12	MCM67A618
Description	64K x 18 Bit Asychronous/Latched Address Fast Static RAM	64K x 18 Bit Asychronous/Latched Address Fast Static RAM	64K x 18 Bit Asychronous/Latched Address Fast Static RAM	64K x 18 Bit Asychronous/Latched Address Fast Static RAM
Maker	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	-
package instruction	PLASTIC, LCC-52	PLASTIC, LCC-52	QCCJ, LDCC52,.8SQ	-
Reach Compliance Code	unknow	unknow	unknow	-
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	-
Maximum access time	10 ns	15 ns	12 ns	-
Other features	BYTE WRITE	BYTE WRITE	BYTE WRITE	-
I/O type	COMMON	COMMON	COMMON	-
JESD-30 code	S-PQCC-J52	S-PQCC-J52	S-PQCC-J52	-
JESD-609 code	e0	e0	e0	-
length	19.1262 mm	19.1262 mm	19.1262 mm	-
memory density	1179648 bi	1179648 bi	1179648 bi	-
Memory IC Type	CACHE TAG SRAM	CACHE TAG SRAM	CACHE TAG SRAM	-
memory width	18	18	18	-
Number of functions	1	1	1	-
Number of ports	1	1	1	-
Number of terminals	52	52	52	-
word count	65536 words	65536 words	65536 words	-
character code	64000	64000	64000	-
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-
Maximum operating temperature	70 °C	70 °C	70 °C	-
organize	64KX18	64KX18	64KX18	-
Output characteristics	3-STATE	3-STATE	3-STATE	-
Exportable	YES	YES	YES	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	QCCJ	QCCJ	QCCJ	-
Encapsulate equivalent code	LDCC52,.8SQ	LDCC52,.8SQ	LDCC52,.8SQ	-
Package shape	SQUARE	SQUARE	SQUARE	-
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	-
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	-
power supply	5 V	5 V	5 V	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	4.57 mm	4.57 mm	4.57 mm	-
Maximum standby current	0.02 A	0.02 A	0.02 A	-
Minimum standby current	4.75 V	4.75 V	4.75 V	-
Maximum slew rate	0.29 mA	0.265 mA	0.28 mA	-
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	-
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	-
Nominal supply voltage (Vsup)	5 V	5 V	5 V	-
surface mount	YES	YES	YES	-
technology	BICMOS	BICMOS	BICMOS	-
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	J BEND	J BEND	J BEND	-
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	-
Terminal location	QUAD	QUAD	QUAD	-
width	19.1262 mm	19.1262 mm	19.1262 mm	-

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