MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM67A618/D
64K x 18 Bit Asynchronous/
Latched Address Fast Static RAM
The MCM67A618 is a 1,179,648 bit latched address static random access
memory organized as 65,536 words of 18 bits, fabricated with Motorola’s high–
performance silicon–gate BiCMOS technology. The device integrates a 64K x 18
SRAM core with advanced peripheral circuitry consisting of address and data in-
put latches, active low chip enable, separate upper and lower byte write strobes,
and a fast output enable. This device has increased output drive capability sup-
ported by multiple power pins.
Address, data in, and chip enable latches are provided. When latch enables
(AL for address and chip enables and DL for data in) are high, the address, data
in, and chip enable latches are in the transparent state. If latch enables are tied
high the device can be used as an asynchronous SRAM. When latch enables are
low the address, data in, and chip enable latches are in the latched state. This
input latch simplifies read and write cycles by guaranteeing address and data–in
hold time in a simple fashion.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits) while UW controls DQ9 – DQ17
(the upper bits).
Six pair of power and ground pins have been utilized and placed on the pack-
age for maximum performance.
The MCM67A618 will be available in a 52–pin plastic leaded chip carrier
(PLCC).
This device is ideally suited for systems that require wide data bus widths,
cache memory, and tag RAMs.
•
•
•
•
•
•
•
•
•
Single 5 V
±
5% Power Supply
Fast Access Times: 10/12/15 ns Max
Byte Writeable via Dual Write Enables
Separate Data Input Latch for Simplified Write Cycles
Address and Chip Enable Input Latches
Common Data Inputs and Data Outputs
Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
MCM67A618
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
A6
A7
E
UW
LW
VCC
V SS
DL
AL
G
A8
A9
A10
DQ9
DQ10
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
3 2 1 52 51 50 49 48 47
46
8
45
9
44
10
43
11
42
12
41
13
40
14
39
15
38
16
37
17
36
18
35
19
34
20 21 22 23 24 25 26 27 28 29 30 31 32 33
A5
A4
A3
A2
A1
A0
V SS
V CC
A15
A14
A13
A12
A11
7 6 5 4
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
AL . . . . . . . . . . . . . . . . . . . . . . Address Latch
DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Higher Byte Write Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be con-
nected for proper operation of the device.
REV 4
5/95
©
Motorola, Inc. 1994
MOTOROLA FAST SRAM
MCM67A618
1
BLOCK DIAGRAM
A0 – A15
16
LATCH
16
MEMORY ARRAY
64K x 18
18
OUTPUT
BUFFER
DQ0 – DQ17
18
18
9
9
WRITE AMP
E
LATCH
CONTROL
18
LATCH
AL
LW
UW
G
DL
TRUTH TABLE
E
H
L
L
L
L
L
L
L
L
LW
X
X
X
H
H
L
L
L
H
UW
X
X
X
H
H
L
L
H
L
AL*
X
L
H
X
X
X
X
X
X
DL*
X
X
X
X
X
L
H
X
X
G
X
X
X
L
H
X
X
X
X
Mode
Deselected Cycle
Read or Write Using Latched Addresses
Read or Write Using Unlatched Addresses
Read Cycle
Read Cycle
Write Both Bytes Using Latched Data In
Write Both Bytes Using Unlatched Data In
Write Cycle, Lower Byte
Write Cycle, Lower Byte
Supply
Current
ISB
ICC
ICC
ICC
ICC
ICC
ICC
ICC
I/O
Status
High–Z
—
—
Data Out
High–Z
High–Z
High–Z
High–Z
ICC
High–Z
*E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup
*and
hold times for falling edge of DL.
NOTE: This truth table shows the application of each function. Combinations of these functions are valid.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC
Output Current (per I/O)
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature
Symbol
VCC
Vin, Vout
Iout
PD
Tbias
TA
Value
– 0.5 to 7.0
– 0.5 to VCC + 0.5
±
30
1.6
– 10 to + 85
0 to + 70
Unit
V
V
mA
W
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM67A618
2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to VSS = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Input Low Voltage
Symbol
VCC
VIH
VIL
Min
4.75
2.2
– 0.5
*
Max
5.25
VCC + 0.3
**
0.8
Unit
V
V
V
**
VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Output Leakage Current (G = VIH)
AC Standby Current (G = VIH, Iout = 0 mA, All Inputs = VIL and VIH,
VIL = 0.0 V and VIH
≥
3.0 V, Cycle Time
≥
tAVAV min)
AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH,
VIL = 0.0 V and VIH
≥
3.0 V, Cycle Time
≥
tAVAV min)
CMOS Standby Current (E
≥
VCC – 0.2, All Inputs
≥
VCC – 0.2 V or
≤
0.2 V, f = fmax)
Output Low Voltage (IOL = + 8.0 mA)
Output High Voltage (IOH = – 4.0 mA)
Symbol
Ilkg(I)
Ilkg(O)
ICCA10
ICCA12
ICCA15
ISB1
ISB2
VOL
VOH
Min
—
—
—
Max
±
1.0
±
1.0
290
280
265
95
20
0.4
3.3
Unit
µA
µA
mA
—
—
—
2.4
mA
mA
V
V
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance (All Pins Except DQ0 – DQ17)
Input/Output Capacitance (DQ0 – DQ17)
Symbol
Cin
CI/O
Typ
4
6
Max
5
8
Unit
pF
pF
MOTOROLA FAST SRAM
MCM67A618
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
ASYNCHRONOUS READ CYCLE TIMING
(See Notes 1 and 2)
MCM67A618–10
Parameter
Read Cycle Times
Access Times:
Address Valid to Output Valid
E Low to Output Valid
Output Enable Low to Output Valid
Output Hold from Address Change
Output Buffer Control:
E Low to Output Active
G Low to Output Active
E High to Output High–Z
G High to Output High–Z
Power Up Time
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
tELICCA
—
—
—
4
3
1
2
2
0
10
10
5
—
—
—
5
5
—
—
—
—
4
3
1
2
2
0
12
12
6
—
—
—
6
6
—
—
—
—
4
3
1
2
2
0
15
15
7
—
—
—
7
7
—
ns
ns
ns
5
Symbol
tAVAV
Min
10
Max
—
MCM67A618–12
Min
12
Max
—
MCM67A618–15
Min
15
Max
—
Unit
ns
ns
Notes
3
4
NOTES:
1. AL and DL are equal to VIH for all asynchronous cycles.
2. Both Write Enable signals (LW, UW) are equal to VIH for all read cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. Transition is measured
±
500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tEHQZ is less than tELQX and tGHQZ is less than tGLQX for a given device.
AC TEST LOADS
+5V
480
Ω
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
OUTPUT
255
Ω
5 pF
Figure 1A
Figure 1B
MCM67A618
4
MOTOROLA FAST SRAM
ASYNCHRONOUS READ CYCLES
AL (ADDRESS
LATCH)
A (ADDRESS)
A1
tAVAV
A2
A3
E
(CHIP ENABLE)
tELQV
tELQX
Q (DATA OUT)
tAVQV
tAXQX
Q(A1)
tGHQZ
Q(A2)
tGLQX
tGLQV
G
(OUTPUT ENABLE)
LW, UW
(WRITE ENABLE)
DL
(DATA LATCH)
tEHQZ
Q(A3)
MOTOROLA FAST SRAM
MCM67A618
5
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