MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6706R/D
32K x 8 Bit Static Random Access
Memory
The MCM6706R is a 262,144 bit static random access memory organized as
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
•
•
•
•
•
Single 5.0 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706R–6 = 6 ns
MCM6706R–7 = 7 ns
MCM6706R–8 = 8 ns
•
Center Power and I/O Pins for Reduced Noise
MCM6706R
J PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
A0
A1
A2
A3
E
DQ0
DQ1
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A14
A13
A12
G
DQ7
DQ6
VSS
VCC
DQ5
DQ4
A11
A10
A9
A8
NC
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
DQ0
INPUT
DATA
CONTROL
DQ7
A
COLUMN I/O
COLUMN DECODER
ROW
DECODER
MEMORY
MATRIX
512 ROWS x 64 x 8
COLUMNS
VCC
VSS
VSS
DQ2
DQ3
W
A4
A5
A6
A7
PIN NAMES
A0 – A14 . . . . . . . . . . . . . . . . . . Address
W . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ7 . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . No Connection
A
A
A
A
A
E
W
G
REV 1
5/95
©
Motorola, Inc. 1995
MOTOROLA FAST SRAM
MCM6706R
1
TRUTH TABLE
E
H
L
L
L
G
X
H
L
X
W
X
H
H
L
Mode
Not Selected
Read
Read
Write
I/O Pin
High–Z
High–Z
Dout
Din
Cycle
—
—
Read Cycle
Write Cycle
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Output Current
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature — Plastic
Symbol
VCC
Vin, Vout
Iout
PD
Tbias
TA
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
±
30
2.0
– 10 to + 85
0 to + 70
Unit
V
V
mA
W
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Input Low Voltage
Symbol
VCC
VIH
VIL
Min
4.5
2.2
– 0.5
**
Typ
5.0
—
—
Max
5.5
VCC + 0.3
*
0.8
Unit
V
V
V
* VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width
≤
2.0 ns) or I
≤
30.0 mA.
** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width
≤
2.0 ns) or I
≤
30.0 mA.
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)
Output High Voltage (IOH = – 4.0 mA)
Output Low Voltage (IOL = + 8.0 mA)
Symbol
Ilkg(I)
Ilkg(O)
VOH
VOL
Min
—
—
2.4
—
Max
±
1.0
±
1.0
—
0.4
Unit
µA
µA
V
V
POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax)
AC Standby Current (E = VIH, VCC = max, f = fmax)
CMOS Standby Current (VCC = max, f = 0 MHz, E
≥
VCC – 0.2 V,
Vin
≤
VSS, or
≥
VCC – 0.2 V)
Symbol
ICCA
ISB1
ISB2
6706R–6
205
95
20
6706R–7
200
90
20
6706R–8
195
85
20
Unit
mA
mA
mA
Notes
1, 2, 3
1, 2. 3
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
MCM6706R
2
MOTOROLA FAST SRAM
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Address Input Capacitance
Control Pin Input Capacitance (E, G, W)
I/O Capacitance
Symbol
Cin
Cin
Cout
Max
5
6
6
Unit
pF
pF
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLE
(See Notes 1 and 2)
MCM6706R–6
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Chip Enable Low to Output Active
Chip Enable High to Output High–Z
Output Enable Low to Output Active
Output Enable High to Output High–Z
Symbol
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
Min
6
—
—
—
3
3
0
0
0
Max
—
6
6
4
—
—
3
—
3
MCM6706R–7
Min
7
—
—
—
3
3
0
0
0
Max
—
7
7
4
—
—
3.5
—
3.5
MCM6706R–8
Min
8
—
—
—
3
3
0
0
0
Max
—
8
8
4
—
—
4
—
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 ,5, 6
4, 5, 6
4, 5, 6
4, 5, 6
Notes
3
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
8. Addresses valid prior to or coincident with E going low.
AC TEST LOADS
+5 V
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
OUTPUT
255
Ω
5 pF
480
Ω
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM6706R
3
READ CYCLE 1
(See Note 7)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
tAVQV
DATA VALID
READ CYCLE 2
(See Note 8)
tAVAV
A (ADDRESS)
tELQV
E (CHIP ENABLE)
tELQX
G (OUTPUT ENABLE)
tGLQX
Q (DATA OUT)
tAVQV
tGLQV
DATA VALID
tGHQZ
tEHQZ
MCM6706R
4
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
MCM6706R–6
Parameter
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
Symbol
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
Min
6
0
6
6
3
0
0
3
0
Max
—
—
—
—
—
—
3.5
—
—
MCM6706R–7
Min
7
0
7
7
3.5
0
0
3
0
Max
—
—
—
—
—
—
3.5
—
—
MCM6706R–8
Min
8
0
8
8
4
0
0
3
0
Max
—
—
—
—
—
—
4
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5, 6
4, 5, 6
Notes
3
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV
A (ADDRESS)
tAVWH
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tAVWL
tWHAX
tDVWH
DATA VALID
tWHDX
D (DATA IN)
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tWHQX
MOTOROLA FAST SRAM
MCM6706R
5
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