MCM63P631ATQ66 datasheet, PDF - EEWORLD Datasheet

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MCM63P631ATQ66: Description64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM; Categorystorage storage; File Size149KB，16 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM63P631ATQ66 Overview

64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P631ATQ66 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	8 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	2097152 bi
Memory IC Type	CACHE SRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	100
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX32
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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MCM63P631A

64K x 32 Bit Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM63P631A is a 2M bit synchronous fast static RAM designed to pro-

vide a burstable, high performance, secondary cache for the 68K Family, Pow-

erPC™, and Pentium™ microprocessors. It is organized as 64K words of 32 bits

each. This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

control with the use of an external clock (K). CMOS circuitry reduces the overall

power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-

trolled through positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63P631A (burst sequence

operates in linear or interleaved mode dependent upon state of LBO) and con-

trolled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable SW are provided to allow writes to either individual bytes or to

all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

The MCM63P631A operates from a 3.3 V power supply, all inputs and outputs

are LVTTL compatible.

•

MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)

MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)

MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)

MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)

•

Single 3.3 V + 10%, – 5% Power Supply

•

ADSP, ADSC, and ADV Burst Control Pins

•

Selectable Burst Sequencing Order (Linear/Interleaved)

•

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

•

Sleep Mode (ZZ)

•

PB1 Version 2.0 Compatible

•

Single–Cycle Deselect Timing

•

JEDEC Standard 100–Pin TQFP Package

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

Pentium is a trademark of Intel Corp.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

9/30/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM63P631A

MCM63P631ATQ66 Related Products

	MCM63P631ATQ66	MCM63P631ATQ75R	MCM63P631ATQ75	MCM63P631ATQ66R	MCM63P631ATQ117R	MCM63P631ATQ117	MCM63P631ATQ100R	MCM63P631A	MCM63P631ATQ100
Description	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
Maker	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	-	Motorola ( NXP )
Parts packaging code	QFP	QFP	QFP	QFP	QFP	-	-	-	QFP
package instruction	LQFP,	LQFP,	LQFP,	LQFP,	LQFP,	TQFP-100	TQFP-100	-	LQFP,
Contacts	100	100	100	100	100	-	-	-	100
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow	unknow	unknown	-	unknow
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	-	3A991.B.2.A
Maximum access time	8 ns	7 ns	7 ns	8 ns	4.5 ns	4.5 ns	4.5 ns	-	4.5 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	-	R-PQFP-G100
length	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	-	20 mm
memory density	2097152 bi	2097152 bi	2097152 bi	2097152 bi	2097152 bi	2097152 bi	2097152 bit	-	2097152 bi
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	-	CACHE SRAM
memory width	32	32	32	32	32	32	32	-	32
Number of functions	1	1	1	1	1	1	1	-	1
Number of ports	1	1	1	1	1	1	1	-	1
Number of terminals	100	100	100	100	100	100	100	-	100
word count	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	-	65536 words
character code	64000	64000	64000	64000	64000	64000	64000	-	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	-	70 °C
organize	64KX32	64KX32	64KX32	64KX32	64KX32	64KX32	64KX32	-	64KX32
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	-	3-STATE
Exportable	YES	YES	YES	YES	YES	YES	YES	-	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	-	LQFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	-	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	-	1.6 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	-	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	-	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	-	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	-	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	-	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	-	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	-	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	-	14 mm

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