MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MCM63P631A
64K x 32 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P631A is a 2M bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the 68K Family, Pow-
erPC™, and Pentium™ microprocessors. It is organized as 64K words of 32 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). CMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-
trolled through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P631A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO) and con-
trolled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable SW are provided to allow writes to either individual bytes or to
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P631A operates from a 3.3 V power supply, all inputs and outputs
are LVTTL compatible.
•
MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)
MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)
MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)
•
Single 3.3 V + 10%, – 5% Power Supply
•
ADSP, ADSC, and ADV Burst Control Pins
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Internally Self–Timed Write Cycle
•
Byte Write and Global Write Control
•
Sleep Mode (ZZ)
•
PB1 Version 2.0 Compatible
•
Single–Cycle Deselect Timing
•
JEDEC Standard 100–Pin TQFP Package
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Pentium is a trademark of Intel Corp.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
9/30/97
©
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM63P631A
1
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
ADSC
ADSP
K2
BURST
COUNTER
CLR
2
2
16
64K x 32 ARRAY
SA
SA1
SA0
ADDRESS
REGISTER
16
14
SGW
SW
WRITE
REGISTER
a
32
32
SBa
SBb
WRITE
REGISTER
b
4
WRITE
REGISTER
c
DATA–IN
REGISTER
K
DATA–OUT
REGISTER
SBc
WRITE
REGISTER
d
SBd
K2
K
SE1
SE2
SE3
G
ZZ
ENABLE
REGISTER
ENABLE
REGISTER
DQa – DQd
MCM63P631A
2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
V DD
VSS
K
SGW
SW
G
ADSC
ADSP
ADV
SA
SA
NC
DQc
DQc
VDD
VSS
DQc
DQc
DQc
DQc
VSS
VDD
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDD
VSS
DQd
DQd
DQd
DQd
VSS
VDD
DQd
DQd
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
78
3
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
NC
NC
DQb
DQb
VDD
VSS
DQb
DQb
DQb
DQb
VSS
VDD
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDD
VSS
DQa
DQa
DQa
DQa
VSS
VDD
DQa
DQa
NC
MOTOROLA FAST SRAM
MCM63P631A
3
PIN DESCRIPTIONS
Pin Locations
85
Symbol
ADSC
Type
Input
Description
Synchronous Address Status Controller: Active low, is used to latch a
new external address. Used to initiate a READ, WRITE or chip
deselect.
Synchronous Address Status Processor: Initiates READ or chip
deselect cycle (exception — chip deselect does not occur when ADSP
is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
84
ADSP
Input
83
(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29
86
89
31
ADV
DQx
Input
I/O
G
K
LBO
Input
Input
Input
Asynchronous Output Enable.
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
Power Supply: 3.3 V + 10%, – 5%.
Ground.
No Connection: There is no connection to the chip.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 81, 82, 99, 100
36, 37
SA
SA1, SA0
Input
Input
93, 94, 95, 96
(a) (b) (c) (d)
98
SBx
SE1
Input
Input
97
92
88
SE2
SE3
SGW
Input
Input
Input
87
SW
Input
64
ZZ
Input
4, 11, 15, 20, 27, 41,
54, 61, 65, 70, 77, 91
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
1, 14, 16, 30, 38, 39,
42, 43, 50, 51, 66, 80
VDD
VSS
NC
Supply
Supply
—
MCM63P631A
4
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 through 5)
Next Cycle
Deselect
Deselect
Deselect
Deselect
Deselect
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
Address
Used
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
External
Next
Next
Current
Current
SE1
1
0
0
X
X
0
0
X
X
1
1
X
X
1
1
0
X
1
X
1
SE2
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
1
X
X
X
X
SE3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
0
X
X
X
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
1
X
1
X
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
0
1
1
1
1
ADV
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
0
0
1
1
G3
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
X
X
X
X
X
DQx
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
High–Z
High–Z
High–Z
High–Z
Write 2, 4
X
X
X
X
X
READ5
READ5
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This READ assumes the RAM was previously deselected.
MOTOROLA FAST SRAM
MCM63P631A
5
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