Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances
of resistors used.
2
Based on an end-point calculation using 10 mA and 150 mA loads. See Figure 8 for typical load regulation performance for loads less than 10 mA.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.5 V.
4
Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of its nominal value.
5
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
Rev. 0 | Page 3 of 16
ADP1710/ADP1711
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
IN to GND
OUT to GND
EN to GND
ADJ/BYP to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
–0.3 V to +6 V
–0.3 V to IN
–0.3 V to +6 V
–0.3 V to +6 V
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
5-Lead TSOT
θ
JA
170
Unit
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
ADP1710/ADP1711
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN
1
GND
2
06310-004
ADP1710
FIXED
TOP VIEW
(Not to Scale)
5
OUT
IN
1
GND
2
ADP1710
ADJUSTABLE
TOP VIEW
(Not to Scale)
5
OUT
IN
1
GND
2
06310-005
ADP1711
TOP VIEW
(Not to Scale)
5
OUT
EN
3
4
NC
EN
3
4
ADJ
EN
3
4
BYP
NC = NO CONNECT
Figure 4. 5-Lead TSOT (UJ-Suffix)
Figure 5. 5-Lead TSOT (UJ-Suffix)
Figure 6. 5-Lead TSOT (UJ-Suffix)
Table 4. Pin Function Descriptions
ADP1710
Fixed
Pin No.
1
2
3
4
4
4
5
5
5
ADP1710
Adjustable
Pin No.
1
2
3
ADP1711
Pin No.
1
2
3
Mnemonic
IN
GND
EN
NC
ADJ
BYP
OUT
Description
Regulator Input Supply. Bypass IN to GND with a 1 μF or greater capacitor.
Ground.
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the
regulator. For automatic startup, connect EN to IN.
No Connect.
Adjust. A resistor divider from OUT to ADJ sets the output voltage.
Connect a 1 nF or greater capacitor (10 nF is recommended) between BYP and GND
to reduce the internal reference noise for low noise applications.
Regulated Output Voltage. Bypass OUT to GND with a 1 μF or greater capacitor.
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FPGA/CPLD
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