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49FCT3805QG

Description
Digital to Analog Converters - DAC 16 Bit,6GSPS RF DAC u0026DDS w/interpolation
Categorysemiconductor    Analog mixed-signal IC   
File Size66KB,7 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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49FCT3805QG Overview

Digital to Analog Converters - DAC 16 Bit,6GSPS RF DAC u0026DDS w/interpolation

49FCT3805QG Parametric

Parameter NameAttribute value
Product CategoryClock Drivers & Distribution
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Multiply / Divide Factor1:5
Output TypeLVCMOS
Max Output Freq50 MHz
Supply Voltage - Max3.6 V
Supply Voltage - Min3 V
Maximum Operating Temperature+ 70 C
Minimum Operating Temperature0 C
Mounting StyleSMD/SMT
Package / CaseQSOP-20
PackagingTube
Height1.47 mm
Input TypeLVCMOS
Length8.7 mm
Operating Supply Current20 mA
Factory Pack Quantity55
TypeClock Buffer/Driver
Width3.8 mm
Unit Weight0.008508 oz
IDT49FCT3805/A
3.3V CMOS BUFFER/CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
BUFFER/CLOCK DRIVER
IDT49FCT3805/A
FEATURES:
DESCRIPTION:
0.5 MICRON CMOS Technology
Guaranteed low skew < 500ps (max.)
Very low duty cycle distortion < 1.0ns (max.)
Very low CMOS power levels
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
V
CC
= 3.3V ± 0.3V
Available in SSOP, SOIC, and QSOP packages
The FCT3805 is a 3.3 volt, non-inverting clock driver built using
advanced dual metal CMOS technology. The device consists of two banks
of drivers, each with a 1:5 fanout and its own output enable control. The
device has a "heartbeat" monitor for diagnostics and PLL driving. The
MON output is identical to all other outputs and complies with the output
specifications in this document. The FCT3805 offers low capacitance inputs
with hysteresis.
The FCT3805 is designed for high speed clock distribution where signal
quality and skew are critical. The FCT3805 also allows single point-to-
point transmission line driving in applications such as address distribution,
where one signal must be distributed to multiple recievers with low skew
and high signal quality.
For more information on using the FCT3805 with two different input
frequencies on bank A and B, please see AN-236.
FUNCTIONAL BLOCK DIAGRAM
OE
A
5
IN
A
OA
1
- OA
5
PIN CONFIGURATION
V
CCA
OA
1
OA
2
OA
3
GND
A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CCB
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
MON
OE
B
IN
B
IN
B
OE
B
5
OB
1
- OB
5
OA
4
OA
5
GND
Q
M ON
OE
A
IN
A
SOIC/ SSOP/ QSOP
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
c
2005
Integrated Device Technology, Inc.
MAY 2010
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