Steady State Output Current..................................................................................................................................................± 0.2A
...................................................................................................................................-65 to 150°C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183°C, 230°C peak
Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < T
A
< 85°C, -40°C < T
J
< 150°C,
3V < V
C
< 20V, 8.2V < V
CC
< 20V, R
T
= 12kΩ, C
T
= 390pF.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Under Voltage Lockout
START Threshold (CS51021/22)
START Threshold (CS51023/24)
STOP Threshold
Hysteresis (CS51021/22)
Hysteresis (CS51023/24)
I
CC
@ Startup (CS51021/22)
I
CC
@ Startup (CS51023/24)
I
CC
Operating (CS51021/23)
I
CC
Operating (CS51022/24)
I
C
Operating
s
Voltage Reference
Initial Accuracy
Total Accuracy
Line Regulation
Load Regulation
NOISE Voltage
OP Life Shift
FAULT Voltage
OK Voltage
OK Hysteresis
Current Limit
s
Error Amplifier
Initial Accuracy
Reference Voltage
V
FB
Leakage Current
Open Loop Gain
Unity Gain Bandwidth
COMP Sink Current
COMP Source Current
T
A
=25°C, I
REF
= 2mA, V
CC
= 14V,
V
FB
= COMP (Note 1)
V
FB
= COMP
V
FB
= 0V
1.4V < COMP < 4V (Note 1)
(Note 1)
COMP = 1.5V, V
FB
= 2.7V
COMP = 1.5V, V
FB
= 2.3V
2
60
1.5
2
-0.2
2.465
2.440
2.515
2.515
-0.2
90
2.5
6
-0.5
2.565
2.590
-2
V
V
µA
dB
MHz
mA
mA
T
A
= 25C, I
REF
= 2mA, V
CC
= 14V (Note1) 4.95
1mA<I
REF
<10mA
8.2V < V
CC
< 18V, I
REF
= 2mA
1mA < I
REF
< 10mA
(Note 1)
T=1000 Hours (Note 1)
Force V
REF
Force V
REF
Force V
REF
Force V
REF
4.9
5
5
6
6
5.05
5.15
20
15
V
V
mV
mV
uV
mV
V
V
mV
mA
Includes 1nF Load
7.95
12.4
7.4
0.50
4
V
CC
< UV
START
Threshold
V
CC
< UV
START
Threshold
8.25
13
7.7
0.75
5
40
45
7
6
7
8.8
13.4
8.2
1.00
6
75
75
9
8
12
V
V
V
V
V
µA
µA
mA
mA
mA
.92
×
V
REF
50
4
20
.95
×
V
REF
.97
×
V
REF
.94
×
V
REF
.96
×
V
REF
.98
×
V
REF
50
-20
105
160
Electrical Characteristics: -40°C < T
A
< 85°C, -40°C < T
J
< 150°C, 3V < V
C
< 20V, 8.2V < V
CC
< 20V,
R
T
= 12kΩ, C
T
= 390pF, unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS51021/22/23/24
s
Error Amplifier continued
COMP High Voltage
COMP Low Voltage
PS Ripple Rejection
SS Clamp, V
COMP
I
LIM(SET)
Clamp
s
Oscillator
Accuracy
Voltage Stability
Temperature Stability
Min Charge & Discharge Time
Duty Cycle Accuracy
Peak Voltage
Valley Voltage
Valley Clamp Voltage
Discharge Current
Discharge Current
s
Synchronization (CS51021/23)
Input Threshold
Output Pulsewidth
Output High Voltage
Input Resistance
Drive Delay
Output Drive Current
s
SLEEP (CS51022/24)
SLEEP Input Threshold
SLEEP Input Current
I
CC
@ SLEEP
s
GATE Driver
HIGH Voltage
LOW Voltage
HIGH Voltage Clamp
LOW Voltage Clamp
Peak Current
UVL Leakage
RISE Time
FALL Time
Measure V
C
-GATE, V
C
= 10V, 150mA Load
Measure GATE-PGnd, 150mA SINK
V
C
= 20V, 1nF
Measured at 10mA Output Current
V
C
= 20V, 1nF (Note 1)
V
C
= 20V, measured at 0V
Load = 1nF, 1V < GATE < 9V,
V
C
= 20V, T
A
= 25°C
Load = 1nF, 9V > GATE > 1V, V
C
= 20V
11
1.5
1.2
13.5
0.6
1
-1
60
15
2.2
1.5
16
0.8
-50
100
40
V
V
V
V
A
µA
ns
ns
Active High
V
SLEEP
= 4V
V
CC
≤
15V
1.0
11
1.5
25
50
2.7
46
100
V
µA
µA
1.0
160
3.5
35
80
1.25
1.5
260
4.3
70
120
2
2.7
360
4.8
140
150
3.5
V
ns
V
kΩ
ns
mA
R
T
= 12k, C
T
= 390pF
Delta Frequency 8.2V < V
CC
< 20V
T
MIN
< T
A
< T
MAX
(Note1)
(Note1)
R
T
= 12k, C
T
= 390pF
(Note 1)
(Note 1)
10k Resistor to ground on R
T
C
T
T
A
=25°C (Note 1)
0.333
70
230
255
2
8
77
3
1.5
1.4
1
1
83
280
3
kHz
%
%
µs
%
V
V
V
mA
mA
V
FB
= 2.3V
V
FB
= 2.7V
FREQ = 120Hz (Note 1)
V
SS
=2.5V, V
FB
= 0V, I
SET
= 2V
(Note 1)
4.35
0.4
60
2.4
0.95
4.8
0.8
85
2.5
1
5
1.2
2.6
1.15
V
V
dB
V
V
1.2
0.8
0.925
1.6
1.2
1.075
I
SYNC
= 100µA
(Note 1)
SYNC to GATE RESET
1k Load
3
CS51021/22/23/24
Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < T
A
< 85°C, -40°C < T
J
< 150°C,
3V < V
C
< 20V, 8.2V < V
CC
< 20V, R
T
= 12kΩ, C
T
= 390pF.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
SLOPE Compensation
Charge Current
COMP Gain
Discharge Voltage
s
Current Sense
OFFSET Voltage
Blanking Time
Blanking Disable Voltage
Second Current Threshold Gain
I
SENSE
Input Resistance
Minimum On Time
Gain
s
OV & UV Voltage Monitors
OV Monitor Threshold
OV Hysteresis Current
UV Monitor Threshold
UV Monitor Hysteresis
s
SOFT START (SS)
Charge Current
Discharge Current
Charge Voltage, V
SS
Discharge Voltage, V
SS
Note 1: Guaranteed by Design, not 100% tested in production.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
SLOPE = 2V
Fraction of slope voltage added
to I
SENSE
(Note 1)
SYNC = 0V
-63
0.095
-53
0.100
0.1
-43
0.105
0.2
µA
V/V
V
(Note 1)
Adjust V
FB
0.09
1.8
1.21
0.10
55
2
1.33
5
70
0.80
0.11
160
2.2
1.45
110
0.82
V
ns
V
V/V
kΩ
ns
V/V
GATE High to Low
(Note 1)
30
0.78
2.4
-10
1.38
25
2.5
-12.5
1.45
75
2.6
-15
1.52
100
V
µA
V
mV
SS = 2V
SS = 2V
-70
250
4.4
0.25
-55
1000
4.7
0.27
-40
5
0.30
µA
µA
V
V
16L PDIP & SO Narrow
1
2
3
3
GATE
I
SENSE
SYNC
(CS51021/23)
SLEEP
(CS51022/24)
SLOPE
UV
OV
External power switch driver with 1.0A peak capability.
Current sense amplifier input.
Bi-directional synchronization. Locks to the highest frequency.
Active high chip disable. In sleep mode, V
REF
and GATE are
turned off.
Additional slope to the current sense signal. Internal current
source charges the external capacitor.
Undervoltage protection monitor.
Overvoltage protection monitor.
4
5
6
4
CS51021/22/23/24
Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L PDIP & SO Narrow
7
8
R
T
C
T
I
SET
Timing resistor R
T
and capacitor C
T
determine oscillator frequen-
cy and maximum duty cycle, D
MAX
.
Voltage at this pin sets pulse-by-pulse overcurrent threshold, and
second threshold (1.33 times higher) with Soft Start retrigger (hic-
cup mode).
Feedback voltage input. Connected to the error amplifier invert-
ing input.
Error amplifier output. Frequency compensation network is usu-
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