• CY7C109B is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009B is
available in a 300-mil-wide SOJ package
Functional Description
[1]
The CY7C109B/CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW
Output Enable (OE), and tri-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE
1
) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE
2
) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then
written into the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
CY7C109B is available in standard 400-mil-wide SOJ and 32-
pin TSOP type I packages. The CY7C1009B is available in a
300-mil-wide SOJ package. The CY7C109B and CY7C1009B
are functionally equivalent in all other respects
Logic Block Diagram
Pin Configurations
[2]
SOJ
Top View
NC
A
16
A
14
A
12
A7
A6
A5
I/O
0
INPUT BUFFER
A4
A3
A2
A1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
128K x 8
ARRAY
I/O
0
I/O
1
I/O
2
GND
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
I/O
3
I/O
4
I/O
5
CE
1
CE
2
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
TSOP I
Top View
(not to scale)
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. NC pins are not connected on the die.
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Cypress Semiconductor Corporation
Document #: 38-05038 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 3, 2006
CY7C109B
CY7C1009B
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Maximum CMOS Standby Current (L)
7C109B-12
7C1009B-12
12
90
10
7C109B-15
7C1009B-15
15
80
10
2
7C109B-20
7C1009B-20
20
75
10
Unit
ns
mA
mA
mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input
Voltage
[3]
.................................–0.5V
to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
−40°C
to +85°C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C109B-12
7C1009B-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Test Conditions
Min.
2.4
0.4
2.2
–0.3
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
–1
–5
V
CC
+ 0.3
0.8
+1
+5
90
45
2.2
–0.3
–1
–5
Max.
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
7C109B-15
7C1009B-15
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
80
40
2.2
–0.3
–1
–5
Max.
7C109B-20
7C1009B-20
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
75
30
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Automatic CE
Max. V
CC
, CE
1
> V
IH
Power-Down Current or CE
2
< V
IL
,V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
—TTL Inputs
Automatic CE
Max. V
CC
,
Power-Down Current CE
1
> V
CC
– 0.3V,
—CMOS Inputs
or CE
2
< 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
L
I
SB2
10
10
2
10
mA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
9
8
Unit
pF
pF
Notes:
3. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05038 Rev. *C
Page 2 of 10
CY7C109B
CY7C1009B
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 480Ω
R1 480Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
Equivalent to:
R2
255Ω
GND
≤
3 ns
3.0V
90%
10%
90%
10%
≤
3 ns
ALL INPUT PULSES
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics
[5]
7C109B-12
7C1009B-12
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[7]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[6, 7]
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
CE
1
HIGH to Power-Down, CE
2
LOW to Power-Down
Write Cycle Time
[9]
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
12
10
10
0
0
10
7
0
3
6
0
12
15
12
12
0
0
12
8
0
3
7
3
6
0
15
20
15
15
0
0
12
10
0
3
8
0
6
3
7
0
20
3
12
6
0
7
3
8
12
12
3
15
7
0
8
15
15
3
20
8
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C109B-15
7C1009B-15
Min.
Max.
7C109B-20
7C1009B-20
Min.
Max.
Unit
Write Cycle
[8]
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05038 Rev. *C
Page 3 of 10
CY7C109B
CY7C1009B
Data Retention Characteristics
Over the Operating Range (Low
Power version only)
Parameter
V
DR
I
CCDR
t
CDR
t
R
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Conditions
No input may exceed V
CC
+ 0.5V
V
CC
= V
DR
= 2.0V,
CE
1
> V
CC
– 0.3V or CE
2
< 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Min.
2.0
150
0
200
Max.
Unit
V
µA
ns
µs
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
CE
V
DR
>
2V
4.5V
t
R
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[11, 12]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
I
CC
HIGH
IMPEDANCE
Notes:
10. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
Document #: 38-05038 Rev. *C
Page 4 of 10
CY7C109B
CY7C1009B
Switching Waveforms
(continued)
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[13, 14]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
t
HD
t
HA
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[13, 14]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 15
t
HZOE
DATA
IN
VALID
t
HD
Notes:
13. Data I/O is high impedance if OE = V
IH
.
14. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
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