MC74F378D datasheet, PDF - EEWORLD Datasheet

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MC74F378D: DescriptionPARALLEL D REGISTER WITH ENABLE; Categorylogic logic; File Size32KB，3 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MC74F378D Overview

PARALLEL D REGISTER WITH ENABLE

MC74F378D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	unknow
Other features	WITH HOLD MODE
series	F/FAST
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	9.9 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Su	80000000 Hz
MaximumI(ol)	0.02 A
Number of digits	6
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	45 mA
propagation delay (tpd)	9.5 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	3.9 mm
minfmax	80 MHz

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MC54/74F378

PARALLEL D REGISTER

WITH ENABLE

The MC54/74F378 is a 6-bit register with a buffered common enable. This

device is similar to the F174 but with common Enable rather than common

Master Reset.

The F378 consists of six edge-triggered D-type flip-flops with individual D

inputs and Q outputs. The Clock (CP) and Enable (E) inputs are common to

all flip-flops.

When the E input is LOW, new data is entered into the register on the LOW-

to-HIGH transition of the CP input. When the E input is HIGH the register will

retain the present data independent of the CP input. This circuit is designed

to prevent false clocking by transitions on the E input..

PARALLEL D REGISTER

WITH ENABLE

FAST™ SCHOTTKY TTL

•

6-Bit High-Speed Parallel Register

Positive Edge-Triggered D-Type Inputs

Fully Buffered Common Clock and Enable Inputs

Input Clamp Diodes Limit High-Speed Termination Effects

CONNECTION DIAGRAM

(TOP VIEW)

VCC

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

D SUFFIX

SOIC

CASE 751B-03

GND

ORDERING INFORMATION

MC54FXXXJ

MC74FXXXN

MC74FXXXD

Ceramic

Plastic

SOIC

FUNCTION TABLE

Inputs

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

Output

No Change

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

FAST AND LS TTL DATA

4-173

MC74F378D Related Products

	MC74F378D	MC74F378	MC74F378N	MC54F378
Description	PARALLEL D REGISTER WITH ENABLE	PARALLEL D REGISTER WITH ENABLE	PARALLEL D REGISTER WITH ENABLE	PARALLEL D REGISTER WITH ENABLE

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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