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MC74F378N

Description
PARALLEL D REGISTER WITH ENABLE
Categorylogic    logic   
File Size32KB,3 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
Download Datasheet Parametric Compare View All

MC74F378N Overview

PARALLEL D REGISTER WITH ENABLE

MC74F378N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMotorola ( NXP )
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
Other featuresWITH HOLD MODE
seriesF/FAST
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.175 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su80000000 Hz
MaximumI(ol)0.02 A
Number of digits6
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)45 mA
propagation delay (tpd)9.5 ns
Certification statusNot Qualified
Maximum seat height4.44 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax80 MHz
MC54/74F378
PARALLEL D REGISTER
WITH ENABLE
The MC54/74F378 is a 6-bit register with a buffered common enable. This
device is similar to the F174 but with common Enable rather than common
Master Reset.
The F378 consists of six edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The Clock (CP) and Enable (E) inputs are common to
all flip-flops.
When the E input is LOW, new data is entered into the register on the LOW-
to-HIGH transition of the CP input. When the E input is HIGH the register will
retain the present data independent of the CP input. This circuit is designed
to prevent false clocking by transitions on the E input..
PARALLEL D REGISTER
WITH ENABLE
FAST™ SCHOTTKY TTL
6-Bit High-Speed Parallel Register
Positive Edge-Triggered D-Type Inputs
Fully Buffered Common Clock and Enable Inputs
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM
(TOP VIEW)
VCC
16
Q5
15
D5
14
D4
13
Q4
12
D3
11
Q3
10
CP
9
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
1
E
2
Q0
3
D0
4
D1
5
Q1
6
D2
7
Q2
8
GND
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
FUNCTION TABLE
Inputs
E
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
Output
Dn
X
H
L
Qn
No Change
H
L
CP
LOGIC SYMBOL
14
13
11
6
4
3
1
D5
D4
D3
D2
D1
D0
E
Q5
Q4
Q3
Q2
Q1
Q0
CP
9
15
12
10
7
5
2
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
4-173

MC74F378N Related Products

MC74F378N MC74F378 MC74F378D MC54F378
Description PARALLEL D REGISTER WITH ENABLE PARALLEL D REGISTER WITH ENABLE PARALLEL D REGISTER WITH ENABLE PARALLEL D REGISTER WITH ENABLE

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