are constructed from four 512K x 8 SRAMs in plastic sur-
face-mount packages on an epoxy laminate board with pins.
On-board decoding selects one of the SRAMs from the
high-order address lines, keeping the remaining devices in
standby mode for minimum power consumption.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When MS and WE inputs
are both LOW, data on the eight data input/output pins is writ-
ten into the memory location specified on the address pins.
Reading the device is accomplished by selecting the device
and enabling the outputs MS and OE active LOW while WE
remains inactive or HIGH. Under these conditions, the content
of the location addressed by the information on the address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the module is selected, outputs are enabled, and write enable
(WE) is HIGH.
Functional Description
The CYM1481A is a high-performance 16-megabit static RAM
module organized as 2048K words by 8 bits. These modules
Logic Block Diagram
A
0
–A
18
19
Pin Configuration
SIP
A
19
V
CC
WE
I/O
2
I/O
3
I/O
0
A
1
A
2
A
3
A
4
GND
I/O
5
A
10
A
11
A
5
A
13
A
14
A
20
MS
A
15
A
16
A
12
A
18
A
6
I/O
1
GND
A
0
A
7
A
8
A
9
I/O
7
I/O
4
I/O
6
A
17
I/O
0
–I/O
7
V
CC
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Top View
512K x 8
SRAM
OE
WE
A
19
–A
20
2
1 of 4
DECODER
512K x 8
SRAM
MS
512K x 8
SRAM
512K x 8
SRAM
8
1481-1
/
Selection Guide
CYM1481A
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
70
110
64
85
110
64
100
110
64
120
110
64
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 • 408-943-2600
October 1990 - Revised April 16, 2001
CYM1481A
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature –55°C to +125°C
Ambient Temperature with
Power Applied0°C to +70°C
Supply Voltage to Ground Potential–0.3V to +7.0V
DC Voltage Applied to Outputs
in High Z State–0.3V to +7.0V
Range
Commercial
DC Input Voltage–0.3V to +7.0V
Output Current into Outputs (LOW)20 mA
Operating Range
Ambient
Temperature
0°C to +70°C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
1481A
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Automatic MS
Power-Down Current
Automatic MS
Power-Down Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
Max. V
CC
, MS > V
IH
,
Min. Duty Cycle = 100%
Max. V
CC
, MS > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V, or V
IN
<
0.2V
Standard
L Version
–100, –120
L Version
–85
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= Min., I
OL
= 2.0 mA
2.2
–0.3
–20
–20
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+20
+20
110
64
32
500
1600
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
µA
µA
V
CC
Operating Supply Current V
CC
= Max., MS < V
IL
, I
OUT
= 0 mA
Capacitance
[1]
Parameter
C
INA
C
INB
C
OUT
Description
Input Capacitance (A
0–16
, OE, WE)
Input Capacitance (A
17–20
, MS)
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
CYM1481AM
ax.
125
25
165
Unit
pF
pF
pF
Note:
1. Tested on a sample basis.
2
CYM1481A
AC Test Loads and Waveforms
R1 2530
Ω
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
R2
2830Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
2830Ω
R1 2530Ω
3.0V
90%
GND
< 10 ns
10%
90%
10%
< 10 ns
ALL INPUT PULSES
(a)
Equivalent to:
OUTPUT
1481-2
(b)
1481-3
1481-4
THÉVENIN EQUIVALENT
1340Ω
2.64V
Switching Characteristics
Over the Operating Range
[2]
1481A-70
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
AMS
t
DOE
t
LZOE
t
HZOE
t
LZMS
t
HZMS
t
WC
t
SMS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
MS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[3]
MS LOW to Low Z
[4]
MS HIGH to High Z
[3, 4]
Write Cycle Time
MS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[3]
WE HIGH to Low Z
5
70
65
65
5
0
65
30
0
30
5
5
30
85
75
75
7
5
65
35
5
30
5
5
30
10
30
100
90
90
7
5
75
40
5
35
5
5
70
40
5
30
10
35
120
100
100
7
5
85
45
5
40
70
70
10
85
45
5
35
10
45
85
85
10
100
50
5
45
100
100
10
120
60
120
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1481A–85
Min.
Max.
1481A–100
Min.
Max.
1481A–120
Min.
Max.
Unit
WRITE CYCLE
[5]
Notes:
2. Test conditions assume signal transition time of 10
µs
or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and
100-pF load capacitance.
3. t
HZOE
, t
HZMS
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±500
mV from steady-state voltage.
4. At any given temperature and voltage condition, t
HZMS
is less than t
LZMS
for any given device. These parameters are guaranteed and not 100% tested.
5. The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CYM1481A
Data Retention Characteristics
(L Version Only)
1481A-70
Parameter
V
DR
I
CCDR
t
CDR[6]
t
R
Description
V
CC
for Retention Data
Data Retention Current V
DR
= 3.0V,
MS > V
CC
– 0.2V,
Chip Deselect to Data
V
IN
> V
CC
– 0.2V or V
IN
Retention Time
< 0.2V
Operation Recovery
Time
Test Conditions
Min.
2
800
0
5
0
5
Max.
1481A–85
Min.
2
800
0
5
Max.
1481A–100
148A1–120
Min.
2
250
Max.
Unit
V
µA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
V
DR
CS
V
IH
V
IH
1481-6
V
DR
> 2V
4.5V
t
R
Switching Waveforms
Read Cycle No. 1
[7, 8]
t
RC
ADDRESS
t
AA
t
OHA
DATAOUT
PREVIOUS DATA VALID
DATA VALID
1481-7
Notes:
6. Guaranteed, not tested.
7. Device is continuously selected. OE, MS = V
IL
.
8. Address valid prior to or coincident with MS transition LOW.
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