MC74AC323
MC74ACT323
Advance Information
8 Input Universal Shift/Storage
Register with Synchronous
Reset and Common I/O Pins
The MC74AC323/74ACT323 is an 8-bit universal shift/storage register with
3-state outputs. Its function is similar to the MC74AC299/74ACT299 with the
exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin count. Separate serial inputs and outputs are provided
for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
•
•
•
•
•
•
Common Parallel I/O for Reduced Pin Count
Additional Serial Inputs and Outputs for Expansion
Four Operating Modes: Shift Left, Shift Right, Load and Store
3-State Outputs for Bus-Oriented Applications
Outputs Source/Sink 24 mA
′ACT323
Has TTL Compatible Inputs
VCC
20
S1
19
DS7
18
Q7
17
I/O7
16
I/O5
15
I/O3
14
I/O1
13
CP
12
DS0
11
8-INPUT UNIVERSAL SHIFT/
STORAGE REGISTER WITH
SYNCHRONOUS RESET
AND COMMON I/O PINS
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
1
S0
2
OE1
3
OE2
4
I/O6
5
I/O4
6
I/O2
7
I/O0
8
Q0
9
SR
10
GND
LOGIC SYMBOL
PIN NAMES
CP
DS0
DS7
S0, S1
SR
OE1, OE2
I/O0–I/O7
Q0, Q7
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Master Reset
3-State Output Enable Inputs
Multipled Parallel Data Inputs or
3-State Parallel Data Outputs
Serial Outputs
S0
S1
CP
1
2
DS0
DS7
Q7
OE
SR Q0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
This document contains information on a new product. Specifications and information herein are subject to change without notice.
FACT DATA
5-1
MC74AC323 MC74ACT323
FUNCTIONAL DESCRIPTION
The MC74AC323/74ACT323 contains eight edge-
triggered D-type flip-flops and the interstage logic necessary
to perform synchronous reset, shift left, shift right, parallel load
and hold operations. The type of operation is determined by S0
and S1 as shown in the Mode Select Table. All flip-flop outputs
are brought out through 3 state buffers to separate I/O pins that
also serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All other
TRUTH TABLE
Inputs
Response
SR
L
H
H
H
H
S1
X
H
L
H
L
S0
X
H
H
L
L
CP
Synchronous Reset; Q0 – Q7 = LOW
Parallel Load; I/On
→
Qn
Shift Right; DS0
→
Q0, Q0
→
Q1, etc.
Shift Left; DS7
→
Q7, Q7
→
Q6, etc.
Hold
X = Immaterial
= LOW-to-HIGH Clock Transition
state changes are also initiated by the LOW-to-HIGH CP
transition. Inputs can change when the clock is in either state
provided only that the recommended setup and hold times,
relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-state
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can still
occur. The 3-state buffers are also disabled by HIGH signals
on both S0 and S1 in preparation for a parallel load operation.
X
H = HIGH Voltage Level
L = LOW Voltage Level
MAXIMUM RATINGS*
Symbol
VCC
Vin
Vout
Iin
Iout
ICC
Tstg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC VCC or GND Current per Output Pin
Storage Temperature
Value
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±20
±50
±50
–65 to +150
Unit
V
V
V
mA
mA
mA
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
VCC @ 3.0 V
tr, tf
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
VCC @ 4.5 V
VCC @ 5.5 V
tr, tf
TJ
TA
IOH
IOL
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
–40
25
VCC @ 4.5 V
VCC @ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
150
40
25
10
ns/V
8.0
140
85
–24
24
°C
°C
mA
mA
ns/V
Typ
5.0
5.0
Max
6.0
5.5
VCC
V
Unit
V
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
FACT DATA
5-3
京公网安备 11010802033920号
EEWORLD
