MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC44251/D
Advance Information
Triple 8-Bit Video ADC
Three-State Outputs
CMOS
The MC44251 contains three independent parallel analog–to–digital flash
converters (ADC). Each ADC consists of 256 latching comparators and an
encoder. Video may be ac or dc coupled. With ac coupling, input clamping
provides for internal dc restoration. The MC44251 also contains a dithering
generator for video processing performance enhancements.
The MC44251 is especially suitable as a front–end converter in TV–picture
digital processing (picture–in–picture, frame storage, etc.). The high speed
conversion rate of the ADC is suitable for video bandwidth of well over 6 MHz.
•
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•
•
•
•
•
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18 MHz Maximum Sampling Rate
Three–State Output Buffers
Output Latching Minimizes Skew
Input Clamps Suitable for RGB and YUV Applications
Built–In Dither Generator with Subsequent Digital Correction
Single 5–Volt Power Supply
Operating Temperature Range: – 40 to + 85°C
VTN and HZ Input Threshold Hysteresis Built–In
44
1
MC44251
FN SUFFIX
44–LEAD PLCC
CASE 777
44
1
FU SUFFIX
44–LEAD QFP
CASE 824A
ORDERING INFORMATION
MC44251FN
MC44251FU
PLCC
QFP
NOTE:
The FN package is not
recommended for new designs.
It is scheduled for phase out
in late 1996.
SIMPLIFIED BLOCK DIAGRAM OF ONE OF THE ADCs
VDD(R)
RTOP
ENCODER
8
Σ
8
LATCH
RMID
8
DATA
OUTPUTS
RBOT
CLOCK
Ibias
ANALOG INPUT
CLAMP
HZ
VTN
MODE
CS
DITHERING
GENERATOR
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 4
7/96
©
Motorola, Inc. 1996
MOTOROLA
MC44251
1
PIN ASSIGNMENTS
PLCC
VDD(D)
B6
B5
B4
VSS(D)
VDD(A)
MODE
B3
B2
B1
B0
QFP
VDD(D)
B6
B5
B4
VSS(D)
VDD(A)
MODE
B3
B2
B1
B0
6
5
4
3
2
1
44
43
42
41
40
VDD(D)
12
R1
13
R2
14
VDD(D)
18
R1
19
R2
20
R3
21
VSS(D)
R3
15
VSS(D)
22
23
24
25
26
27
28
R7
VSS(A)
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD(A), VDD(D),
VDD(R)
Vin
Iin
Iout
Tstg
Characteristic
DC Supply Voltage (referenced to
VSS)
Input Voltage, All Pins
DC Input Current per Pin
DC Output Current per Pin
Storage Temperature Range
Value
– 0.5 to + 6.0
– 0.5 to VDD + 0.5
±
20
±
25
– 65 to + 150
Unit
V
V
mA
mA
°C
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any
voltage higher than maximum rated voltages to
this high–impedance circuit. For proper opera-
tion, Vin and Vout should be constrained to the
range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
NOTE: Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating
Conditions.
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS) (VDD(R) = VDD(A) = VDD(D); Rbias (Pin 33) = 5 kΩ to ground)
OPERATING RANGES
Symbol
VDD(A), VDD(D),
VDD(R)
IDD(A)
IDD(R)
IDD(D)
TA
Power Supply Voltage
Analog Supply Current
Reference Supply Current
Digital Supply Current
Operating Ambient Temperature Range
Characteristic
Min
4.5
—
—
—
– 40
Max
5.5
55
28
5
+ 85
Unit
V
mA
mA
mA
°C
A/D CONVERTER
Symbol
Cin
Vmin
Vmax
Vrange
Gain
DNL
INL
Egain
Eoff
Input Capacitance
See Figure 11
See Figure 11
See Figure 11
See Figure 11 (Note 1)
Differential Nonlinearity (Note 1)
Integral Nonlinearity (Note 1)
Gain Difference (Note 2)
Offset Difference (Notes 1, 2)
Characteristic
Min
—
0.3 x VDD
0.89 x VDD
0.57 x VDD
0.95
—
—
—
—
Max
60
0.36 x VDD
0.93 x VDD
0.59 x VDD
1.0
±
1.0
±
2.0
±
1.0
±
3.0
Unit
pF
V
V
V
LSB
LSB
LSB
%
LSB
MC44251
2
CLOCK
CLOCK
R7
VSS(A)
R5
R6
R4
R5
R6
R4
16
17
18
19
20
21
22
B7
G0
G1
G2
G3
CS
G4
G5
G6
G7
R0
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
Ibias
VSS(R)
Bin
RBOT
Gin
RMID
Rin
RTOP
VDD(R)
VTN
HZ
B7
G0
G1
G2
G3
CS
G4
G5
G6
G7
R0
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Ibias
VSS(R)
Bin
RBOT
Gin
RMID
Rin
RTOP
VDD(R)
VTN
HZ
MOTOROLA
CLOCK INPUT
Symbol
VIH
VIL
IIL
IIH
RATE
twL
twH
tr
tf
Clock Input High Level
Clock Input Low Level
Low Level Input Current
High Level Input Current
Conversion Rate
Clock Low Duration, Figure 1
Clock High Duration, Figure 1
Clock Rise Time (10% to 90%), Figure 1
Clock Fall Time (10% to 90%), Figure 1
Characteristic
Min
4.2
—
—
—
—
27.5
27.5
—
—
Max
—
0.8
±
2.0
±
2.0
18
—
—
15
15
Unit
V
V
µA
µA
ms/s
ns
ns
ns
ns
HZ AND VTN INPUTS
Symbol
VIH
VIL
VHYS
IIL
IIH
tH
Characteristic
HZ and VTN Input Turn–On Threshold Voltage
HZ and VTN Input Turn–Off Threshold Voltage
Hysteresis Voltage
Low Level Input Current
High Level Input Current
HZ High Time, Figure 3
Min
0.56 x VDD
—
0.11 x VDD
—
—
3
Max
—
0.29 x VDD
0.17 x VDD
±
2.0
±
2.0
—
Unit
V
V
V
µA
µA
ns
CHIP SELECT INPUT
Symbol
VIH
VIL
IIN
Input High Level
Clamping Source Current
Input Leakage Current
Characteristic
Min
3.5
—
—
Max
—
1.5
±
2.0
Unit
V
V
µA
CLAMPING NETWORK
(Measured on R,G,B Inputs)
Symbol
Isink
Isource
DICL
Clamping Sink Current
Clamping Source Current
Clamping Current Difference (Note 2)
Clamping Levels (Max. Deviation Compared to Table 1)
Characteristic
Min
2.0
– 5.0
—
—
Max
5.0
– 2.0
0.5
±
1.5
Unit
µA
µA
µA
LSB
n
Vdamp
Symbol
ZTOP
ZBOT
ZMID
RESISTIVE REFERENCE NETWORK
Characteristic
RTOP Output Impedance
RBOT Output Impedance
RMID Output Impedance
Min
28
70
70
Max
48
130
130
Unit
Ω
Ω
Ω
MODE INPUT
Symbol
VIL
VIH
VIZ
IIL
IIH
IIZ
Logical “0” Level
Logical “1” Level
Logical “Open” Level
Input Current at “0” Level
Input Current at “1” Level
Input Current at “Open” Level
Characteristic
Min
0
4.2
2
—
—
—
Max
0.8
VDD(D)
2.8
±
50
±
80
±
50
Unit
V
V
V
µA
µA
µA
MOTOROLA
MC44251
3
DATA OUTPUTS
Symbol
td
IOL
IOH
tQLH, tQHL
IOTR
Characteristic
Delay from Sample Clock to Valid Output, Figure 2
Output Sinking Current at Vout = 0.4 V
Output Sourcing Current at Vout = VDD – 0.1 V
Propagation Delay from the Clock Rising Edge to Valid Data Output
(CL = 15 pF), Figure 1
Maximum Three–State Leakage Current
Min
2.5
2.0
– 0.4
—
—
Max
2.5
—
—
40
±
50
Unit
Cycle
mA
mA
ns
µA
NOTES:
1. Unit “LSB” means ideal LSB (see definitions section).
2. “Difference” means difference between any two converters in the same package.
tr
CLK
90%
50%
10%
twH
tQLH, tQHL
DATA
OUTPUT
50%
tf
VDD(D)
VSS(D)
twL
Figure 1. Clock and Output Timing
PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
B7
G0
G1
G2
G3
CS
G4
G5
G6
G7
R0
VDD(D)
R1
R2
R3
VSS(D)
CLK
R4
R5
R6
R7
VSS(A)
Function
Output Blue, Bit 7 (MSB)
Output Green, Bit 0 (LSB)
Output Green, Bit 1
Output Green, Bit 2
Output Green, Bit 3
Chip Select
Output Green, Bit 4
Output Green, Bit 5
Output Green, Bit 6
Output Green, Bit 7 (MSB)
Output Red, Bit 0 (LSB)
VDD, Digital
Output Red, Bit 1
Output Red, Bit 2
Output Red, Bit 3
VSS, Digital
Clock Input
Output Red, Bit 4
Output Red, Bit 5
Output Red, Bit 6
Output Red, Bit 7 (MSB)
VSS, Analog
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
HZ
VTN
VDD(R)
RTOP
Rin
RMID
Gin
RBOT
Bin
VSS(R)
IBIAS
VDD(A)
MODE
B0
B1
B2
B3
VSS(D)
B4
B5
B6
VDD(D)
Horizontal Sync
Vertical Sync
VDD, reference
Reference Tapping, Top
Analog Input, Red
Reference Tapping, Middle
Analog Input, Green
Reference Tapping, Bottom
Analog Input, Blue
VSS for Reference Voltage
To External Bias Resistor
VDD, Analog
Clamp Level Select Input
Output Blue, Bit 0 (LSB)
Output Blue, Bit 1
Output Blue, Bit 2
Output Blue, Bit 3
VSS, Digital
Output Blue, Bit 4
Output Blue, Bit 5
Output Blue, Bit 6
VDD, Digital
Function
MC44251
4
MOTOROLA
RESISTIVE REFERENCE NETWORK
RTOP (Pin 26)
RBOT (Pin 30)
RMID (Pin 28)
Taps on the reference ladder are pinned out, providing
access to the bottom (R BOT), the top (RTOP), and the middle
scale points. These pins are intended for ac bypassing as
ladder noise may present a problem. The value of the de-
coupling capacitor should not exceed 47 nF. Large capac-
itance values can cause problems because of the amount of
energy stored. When a system containing the MC44251 is
rapidly powered down and up, the capacitor voltage may
exceed the supply voltage during the power up and cause a
latch–up condition. Failure to adequately decouple these
pins can adversely affect the conversion process.
SUPPLY PINS
VDD(A) (Pin 34)
VDD(D) (Pins 44, 12)
VDD(R) (Pin 25)
The three types of supply pins are analog, digital, and
reference. The dc voltage applied to all four pins must be
maintained such that
VDD(A) = VDD(D) = VDD(R).
Each pin must be carefully decoupled to ground as close
to the package as possible, and particular care should be
taken with V DD(R) as any noise present on this pin will
appear in the output data as an equivalent input noise. This
noise will be present on the R in, G in, and B in input pins in a
ratio of 1:1 to the input noise (worst case condition). Noise
reduction can be improved by incorporating choke coil induc-
tors in series with the power supply rails.
ANALOG INPUTS
Rin (Pin 27)
Gin (Pin 29)
Bin (Pin 31)
The analog signals to be converted are input at these pins.
An on–chip clamp circuit for dc restoration is available when
using ac coupling. The clamp circuit operation is activated by
the presence of the signal at the HZ input. This signal is
derived from the composite sync information and must be
coincident with the horizontal sync of the composite video
waveform for proper operation. Yin , U in, and Vin may be used
instead of the RGB signals. In this case the conversion will
be a YUV analog–to–digital conversion.
Ibias (Pin 33)
The comparator bias current is set by connecting an exter-
nal resistor between Ibias and ground. The conversion rate is
guaranteed for a resistor value of 5.1 kΩ
±
5% and will
decrease logarithmically with increased resistance. The
resistor must be placed adjacent to the I bias pin. No decoup-
ling capacitor is allowed on this pin.
DIGITAL OUTPUTS
R0 – R7 (Pins 11, 13 – 15, 18 – 21)
G0 – G7 (Pins 2 – 5, 7 – 10)
B0 – B7 (Pins 36 – 39, 41 – 43, 1)
These pins are the parallel output for the digital value for
the RGB signals. R0 through R7 are the digital equivalent of
the analog RED input, G0 through G7 are equivalent to the
GREEN input, and B0 through B7 are equivalent to the BLUE
input. If YUV analog signals have been input instead of the
RGB signals; the digital outputs will be Y0 through Y7, U0
through U7, and V0 through V7.
DIGITAL INPUTS
Clock (Pin 17)
The analog input voltages to be converted are sensed at
the falling edge of the clock signal and the corresponding
data is present on the digital outputs at the clock signal rising
edge, 2.5 cycles later (see Figure 2).
HZ (Pin 23)
This is the horizontal synchronization input, and is used to
increment the dither generator. The clamp network is also
controlled by HZ to ensure proper dc restoration for R in, G in,
and B in before conversion. Schmitt trigger input is included to
improve noise immunity.
VTN (Pin 24)
The vertical synchronization input, VTN, resets the dither
generator after every second vertical sync pulse (after each
frame). Schmitt trigger input is included to improve noise
immunity.
MODE (Pin 35)
This pin is used to select the proper clamp levels (see
Table 1).
CHIP SELECT (Pin 6)
Chip select is an active low input used to enable the ADC
for data transfers. When the CS is at a high level, the digital
output is forced to a high impedance state.
MOTOROLA
MC44251
5
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