Features
•
Single Voltage Read/Write Operation: 2.65V to 3.6V
•
Access Time – 70 ns
•
Sector Erase Architecture
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•
•
– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 12 µs
Fast Sector Erase Time – 300 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 12 mA Active
– 13 µA Standby
VPP Pin for Write Protection
WP Pin for Sector Protection
RESET Input for Device Initialization
Flexible Sector Protection
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
Common Flash Interface (CFI)
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32-megabit
(2M x 16)
3-volt Only
Flash Memory
AT49BV320C
AT49BV320CT
Description
The AT49BV320C(T) is a 2.7-volt 32-megabit Flash memory organized as 2,097,152
words of 16 bits each. The memory is divided into 71 sectors for erase operations.
The device is offered in a 48-lead TSOP and a 47-ball CBGA package. The device has
CE and OE control signals to avoid any bus contention. This device can be read or
reprogrammed using a single power supply, making it ideally suited for in-system
programming.
Pin Configurations
Pin Name
A0 - A20
CE
OE
WE
RESET
VPP
I/O0 - I/O15
NC
VCCQ
WP
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Write Protection
Data Inputs/Outputs
No Connect
Output Power Supply
Write Protect
Rev. 3372D–FLASH–5/04
1
TSOP Top View
Type 1
CBGA Top View
1
A15
A14
A13
A12
A11
A10
A9
A8
NC
A20
WE
RESET
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
2
3
4
5
6
7
8
A
A13
A11
A10
A12
I/O14
A8
WE
A9
I/O5
I/O6
I/O13
I/O11
I/O12
I/O4
VPP
RST
WP
A18
A20
I/O2
I/O3
VCC
A19
A17
A6
I/O8
I/O9
I/O10
A7
A5
A3
CE
I/O0
I/O1
A4
A2
A1
A0
GND
OE
B
A14
C
A15
D
A16
E
VCCQ I/O15
F
GND
I/O7
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see Flexible Sector Protection section).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory.
The VPP pin provides data protection. When the V
PP
input is below 0.4V, the program and
erase functions are inhibited. When V
PP
is at 1.5V or above, normal program and erase opera-
tions can be performed.
2
AT49BV320C(T)
3372D–FLASH–5/04
AT49BV320C(T)
Block Diagram
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
A0 - A20
INPUT
BUFFER
DATA
REGISTER
IDENTIFIER
REGISTER
STATUS
REGISTER
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
CE
WE
OE
RESET
WP
WRITE STATE
MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
MAIN
MEMORY
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3372D–FLASH–5/04
Device
Operation
READ:
When the AT49BV320C(T) is in the read mode, with CE and OE low and WE high, the
data stored at the memory location determined by the address pins are asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES:
When the device is first powered on, it will be in the read mode. In
order to perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the “Command Definition” table on page 15
(I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are
written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address and data are latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command
sequences are not affected by entering the command sequences.
RESET:
A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read mode,
depending upon the state of the control inputs.
ERASURE:
Before a word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The individual sectors can be erased by using the Sector Erase
command.
SECTOR ERASE:
The device is organized into 71 sectors (SA0 - SA70) that can be individu-
ally erased. The Sector Erase command is a two-bus cycle operation. The sector address and
the D0H Data Input command are latched on the rising edge of WE. The sector erase starts
after the rising edge of WE of the second cycle provided the given sector has not been pro-
tected. The erase operation is internally controlled; it will automatically time to completion. The
maximum time to erase a sector is t
SEC
. An attempt to erase a sector that has been protected
will result in the operation terminating immediately.
WORD PROGRAMMING:
Once a memory sector is erased, it is programmed (to a logical “0”)
on a word-by-word basis. Programming is accomplished via the Internal Device command reg-
ister and is a two-bus cycle operation. The device will automatically generate the required
internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
BP
cycle
time. If the program status bit is a “1”, the device was not able to verify that the program oper-
ation was performed successfully. The status register indicates the programming status. While
the program sequence executes, status bit I/O7 is “0”. While programming, the only valid com-
mands are Read Status Register, Program Suspend and Program Resume.
VPP PIN:
The circuitry of the AT49BV320C(T) is designed so that the device cannot be pro-
grammed or erased if the V
PP
voltage is less that 0.4V. When V
PP
is at 1.5V or above, normal
program and erase operations can be performed. The VPP pin cannot be left floating.
READ STATUS REGISTER:
The status register indicates the status of device operations and
the success/failure of that operation. The Read Status Register command causes subsequent
reads to output data from the status register until another command is issued. To return to
reading from the memory, issue a Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
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AT49BV320C(T)
3372D–FLASH–5/04
AT49BV320C(T)
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status
read, or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing
the preferred operation (see Table 1).
Table 1.
Status Register Bit Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
SR4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
When this bit is set to “1”, WSM has attempted but failed to
program a word
SLS
1
R
0
The V
PP
status bit does not provide continuous indication of VPP
level. The WSM interrogates V
PP
level only after the Program or
Erase command sequences have been entered and informs the
system if V
PP
has not been switched on. The V
PP
is also checked
before the operation is verified by the WSM.
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
This bit is reserved for future use and should be masked out
when polling the status register.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR1 = SECTOR LOCK STATUS
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
SR0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Note:
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
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3372D–FLASH–5/04
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