MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Transparent
Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16 line
decoder with latched inputs. The MC14514B (output active high option)
presents a logical “1” at the selected output, whereas the MC14515B (output
active low option) presents a logical “0” at the selected output. The latches
are R–S type flip–flops which hold the last input data presented prior to the
strobe transition from “1” to “0”. These high and low options of a 4–bit latch/4
to 16 line decoder are constructed with N–channel and P–channel
enhancement mode devices in a single monolithic structure. The latches are
R–S type flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding applications
where low power dissipation and/or high noise immunity is desired.
MC14514B
MC14515B
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
V
V
– 0.5 to + 18.0
±
10
500
– 65 to + 150
Vin, Vout
Iin, Iout
PD
Tstg
Input or Output Voltage (DC or Transient)
0.5 to VDD + 0.5
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
mA
mW
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
DW SUFFIX
SOIC
CASE 751E
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
_
C
TL
Lead Temperature (8–Second Soldering)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
DECODE TRUTH TABLE
(Strobe = 1)*
Data Inputs
Inhibit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Selected Output
MC14514 = Logic “1”
MC14515 = Logic “0”
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
All Outputs = 0, MC14514
All Outputs = 1, MC14515
BLOCK DIAGRAM
VDD = PIN 24
VSS = PIN 12
DATA 1
DATA 2
DATA 3
DATA 4
STROBE
2
3
21
22
A
B
TRANSPARENT
C
LATCH
D
4 TO 16
DECODER
1
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
X = Don’t Care
*Strobe = 0, Data is latched
INHIBIT
REV 3
1/94
23
©
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14514B MC14515B
385
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS)
Characteristic
Symbol
VOL
VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
VIH
5.0
10
15
IOH
Source
5.0
5.0
10
15
IOL
5.0
10
15
15
—
5.0
10
15
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
0.64
1.6
4.2
—
—
—
—
—
—
—
—
—
—
—
—
±
0.1
—
5.0
10
20
– 1.0
– 0.2
– 0.5
– 1.5
0.51
1.3
3.4
—
—
—
—
—
– 1.7
– 0.36
– 0.9
– 3.5
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
—
—
—
—
—
—
—
±
0.1
7.5
5.0
10
20
– 0.7
– 0.14
– 0.35
– 1.1
0.36
0.9
2.4
—
—
—
—
—
—
—
—
—
—
—
—
±
1.0
—
150
300
600
mAdc
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
mAdc
Min
—
—
—
– 55
_
C
25
_
C
125
_
C
Max
Min
—
—
—
Typ #
0
0
0
Max
Min
—
—
—
Max
Unit
Vdc
Output Voltage
Vin = VDD or 0
“0” Level
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Input Capacitance
(Vin = 0)
Quiescent Current
(Per Package)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
VIL
—
—
—
—
—
—
2.25
4.50
6.75
—
—
—
VOH
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Vdc
Sink
Iin
Cin
IDD
µAdc
pF
µAdc
ITL
IT = (1.35
µA/kHz)
f + IDD
IT = (2.70
µA/kHz)
f + IDD
IT = (4.05
µA/kHz)
f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in
µA
(per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MC14514B MC14515B
386
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS*
(CL = 50 pF, TA = 25
_
C)
Characteristic
All Types
Typ #
180
90
65
100
50
40
550
225
150
400
150
100
125
50
38
– 100
– 40
– 30
175
50
38
Symbol
tTLH
VDD
5.0
10
15
tTHL
5.0
10
15
tPLH,
tPHL
5.0
10
15
5.0
10
15
5.0
10
15
th
5.0
10
15
5.0
10
15
—
—
—
—
—
—
—
—
—
250
100
75
– 20
0
10
350
100
75
200
100
80
ns
1100
450
300
ns
800
300
200
ns
—
—
—
—
—
—
—
—
—
ns
Min
—
—
—
Max
360
180
130
ns
Unit
ns
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time; Data, Strobe to S
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.86 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
Inhibit Propagation Delay Times
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 117 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Setup Time
Data to Strobe
tPLH,
tPHL
tsu
Hold Time
Strobe to Data
Strobe Pulse Width
tWH
ns
* The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
VDS
STROBE
INHIBIT
For MC14514B
1. For P–channel: Inhibit = VSS
1.
and D1–D4 constitute
1.
binary code for “output
1.
under test.”
2. For N–channel: Inhibit = VDD
D1
D2
D3
D4
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
VSS
For MC14515B
1. For P–channel: Inhibit = VDD
2. For N–channel: Inhibit = VSS
2.
and D1–D4 constitute binary
2.
code for “output under test.”
ID
EXTERNAL
POWER SUPPLY
Figure 1. Drain Characteristics Test Circuit
MOTOROLA CMOS LOGIC DATA
MC14514B MC14515B
387
VDD
0.01
µF
CERAMIC
ID
24
PULSE
GENERATOR
VDD
500
µF
20 ns
Vin
90%
10%
20 ns
VDD
VSS
D1
S0
D2
D3
D4
STROBE
INHIBIT S15
12
VSS
CL
CL
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
VDD
STROBE
INHIBIT
D1
D2
D3
D4
S0
S1
CL
CL
OUTPUT S0
OUTPUT S1
tTLH
20 ns
90%
50%
tTHL
VDD
VSS
tPHL
VDD
VSS
tTHL
PROGRAMMABLE
PULSE
GENERATOR
INPUT
10%
tPLH
OUTPUT
90%
50%
10%
tTLH
S15
VSS
CL
OUTPUT S15
Figure 3. Switching Time Test Circuit and Waveforms
PIN ASSIGNMENT
ST
D1
D2
S7
S6
S5
S4
S3
S1
S2
S0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
INH
D4
D3
S10
S11
S8
S9
S14
S15
S12
S13
MC14514B MC14515B
388
MOTOROLA CMOS LOGIC DATA
LOGIC DIAGRAM
AB CD
AB CD
AB CD
AB CD
S
Q
A
AB CD
R
B
Q
AB CD
AB CD
AB CD
R
S
Q
C
AB CD
R
S
Q
D
Q
AB CD
AB CD
Q
AB CD
11 S0
9 S1
10 S2
8 S3
7 S4
6 S5
5 S6
4 S7
18 S8
17 S9
20 S10
19 S11
MOTOROLA CMOS LOGIC DATA
S
Q
AB CD
R
Q
AB CD
13 S13
AB CD
AB CD
16 S14
15 S15
14 S12
IN MC14515B ONLY
DATA 1 2
DATA 2 3
DATA 3 21
DATA 4 22
STROBE 1
MC14514B MC14515B
389
INHIBIT 23
京公网安备 11010802033920号
EEWORLD
