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MC100LVEL31D

Description
D Flip-Flop With Set and Reset
Categorylogic    logic   
File Size43KB,4 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
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MC100LVEL31D Overview

D Flip-Flop With Set and Reset

MC100LVEL31D Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMotorola ( NXP )
package instructionPLASTIC, SOIC-8
Reach Compliance Codeunknow
series100LVEL
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.9 mm
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su2900000000 Hz
Number of digits1
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristicsOPEN-EMITTER
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply-3.3 V
Maximum supply current (ICC)38 mA
propagation delay (tpd)0.63 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Trigger typePOSITIVE EDGE
width3.9 mm
minfmax2900 MHz
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
D Flip Flop
With Set and Reset
The MC100LVEL31 is a D flip-flop with set and reset. The device is
functionally equivalent to the EL31 device but operates from a –3.3V (or
+3.3V) supply. With propagation delays and output transition times
essentially equivalent to the EL31, the LVEL31 is ideally suited for those
applications which require the ultimate in AC performance at low power
supply voltages.
Both set and reset inputs are asynchronous, level triggered signals.
Data enters the master portion of the flip-flop when clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock.
MC100LVEL31
8
1
475ps Propagation Delay
2.9GHz Toggle Frequency
75kΩ Internal Input Pulldown Resistors
>2000V ESD Protection
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
S
1
S
8
VCC
D
TRUTH TABLE
S
L
L
H
L
H
R
L
L
L
H
H
CLK
Z
Z
X
X
X
Q
L
H
H
L
Undef
D
2
D
Flip Flop
7
Q
L
H
X
X
X
CLK
3
R
6
Q
R
4
5
VEE
Z = LOW to HIGH Transition
10/96
©
Motorola, Inc. 1996
3–1
REV 0
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