MBM29DL400TC-90 datasheet, PDF

Datasheet> All Categories > MBM29DL400TC-90

Preview

MBM29DL400TC-90: Description4M (512K X 8/256K X 16) BIT; File Size315KB，56 Pages; ManufacturerFUJITSU; Websitehttp://edevice.fujitsu.com/fmd/en/index.html

Download Datasheet Compare View All

MBM29DL400TC-90 Overview

4M (512K X 8/256K X 16) BIT

Preview

Download Datasheet

View All

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20866-2E

FLASH MEMORY

CMOS

4M (512K

8/256K

16) BIT

MBM29DL400TC

-55/-70/-90/-12

/MBM29DL400BC

-55/-70/-90/-12

FEATURES

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

• Simultaneous operations

Read-while-Erase or Read-while-Program

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV400TC/BC)

48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

• Minimum 100,000 program/erase cycles

• High performance

55 ns maximum access time

• Sector erase architecture

Two 16K byte, four 8K bytes, two 32K byte, and six 64K bytes.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V

write inhibit

≤

2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

(Continued)

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29DL400TC

-55/-70/-90/-12

/MBM29DL400BC

-55/-70/-90/-12

GENERAL DESCRIPTION

The MBM29DL400TC/BC are a 4M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each or

256K words of 16 bits each. The MBM29DL400TC/BC are offered in a 48-pin TSOP(I) package. These devices

are designed to be programmed in-system with the standard system 3.0 V V

supply. 12.0 V V

and 5.0 V V

are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM

programmers.

MBM29DL400TC/BC provides simultaneous operation which can read a data while program/erase. The

simultaneous operation architecture provides simultaneous operation by dividing the memory space into two

banks. The device can allow a host system to program or erase in one bank, then immediately and simultaneously

read from the other bank.

The standard MBM29DL400TC/BC offer access times 55 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),

write enable (WE), and output enable (OE) controls.

The MBM29DL400TC/BC are pin and command set compatible with JEDEC standard E

PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29DL400TC/BC are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29DL400TC/BC are erased when shipped from the

factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29DL400TC/BC memories electrically erase the entire chip

or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one

byte/word at a time using the EPROM programming mechanism of hot electron injection.

MBM29DL400TC-90 Related Products

	MBM29DL400TC-90	MBM29DL400TC-55	MBM29DL400TC	MBM29DL400BC-90	MBM29DL400BC-70	MBM29DL400BC-55	MBM29DL400BC	MBM29DL400TC-70	MBM29DL400TC-12	MBM29DL400BC-12
Description	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT	4M (512K X 8/256K X 16) BIT

Recommended Resources

Fire pump (one in use and one in standby) soft start control circuit a

Recording and playback circuit capable of random segment recording

Temperature control circuit connection circuit diagram a

30MHz AGC loop

Construction clock stepper motor drive circuit

Direct FM modulation circuit composed of varactor diodes

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components