GS8342Q18AE-200IT datasheet, PDF

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GS8342Q18AE-200IT: DescriptionDDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165; Categorystorage storage; File Size498KB，34 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8342Q18AE-200IT Overview

DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

GS8342Q18AE-200IT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
Base Number Matches	1

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GS8342Q08/09/18/36AE-278/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write (x36, x18, and x9) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

and 144Mb devices

36Mb SigmaQuad-II

Burst of 2 SRAM

Clocking and Addressing Schemes

167 MHz–278 MHz

1.8 V V

1.8 V and 1.5 V I/O

The GS8342Q08/09/18/36AE SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock quasi independently with the C and C

clock inputs. C and C are also independent single-ended clock

inputs, not differential inputs. If the C clocks are tied high, the

K clocks are routed internally to fire the output registers

instead.

Each internal read and write operation in a SigmaQuad-II B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaQuad-II B2 RAM is always one address pin less than the

advertised index depth (e.g., the 4M x 8 has a 2M addressable

index).

SigmaQuad™ Family Overview

The GS8342Q08/09/18/36AE are built in compliance with

the SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342Q08/09/18/36AE SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Parameter Synopsis

-278

tKHKH

tKHQV

3.6 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

Rev: 1.06c 11/2011

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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