CD4011BKTR datasheet, PDF - EEWORLD Datasheet

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CD4011BKTR: Description4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14; Categorylogic logic; File Size30KB，3 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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CD4011BKTR Overview

4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14

CD4011BKTR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	DFP
package instruction	DFP, FL14,.3
Contacts	14
Reach Compliance Code	not_compliant
series	4000/14000/40000
JESD-30 code	R-CDFP-F14
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.00064 A
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL14,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
Prop。Delay @ Nom-Sup	338 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	MIL-PRF-38535 Class T
Maximum seat height	2.92 mm
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	100k Rad(Si) V
width	6.285 mm
Base Number Matches	1

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CD4011BT

Data Sheet

July 1999

File Number

4620.1

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications Flow

(SAF) devices are fully

tested and guaranteed to 100kRAD total dose. These QML

Class T devices are processed to a standard ﬂow intended

to meet the cost and shorter lead-time needs of large

volume satellite manufacturers, while maintaining a high

level of reliability.

The CD4011BT, Quad 2-Input NAND gate provides the

system designer with direct implementation of the NAND

function and supplements the existing family of CMOS

gates. All inputs and outputs are buffered.

Features

• QML Class T, Per MIL-PRF-38535

• Radiation Performance

- Gamma Dose (γ) 1 x 10

RAD(Si)

- SEP Effective LET > 75 MEV/gm/cm

• Propagation Delay Time = 60ns (typ.) at CL = 50pF,

= 10V

• Buffered Inputs and Outputs

• Standardized Symmetrical Output Characteristics

• 100% Tested for Maximum Quiescent Current at 20V

Speciﬁcations

Speciﬁcations for Rad Hard QML devices are controlled by

the Defense Supply Center in Columbus (DSCC). The SMD

numbers listed below must be used when ordering.

Detailed Electrical Speciﬁcations for the CD4011BT are

contained in SMD 5962-96621.

A “hot-link” is provided from

our website for downloading.

www.intersil.com/quality/manuals.asp

Intersil’s Quality Management Plan (QM Plan), listing all

Class T screening operations, is also available on our

website.

www.intersil.com/quality/manuals.asp

• 5V, 10V and 15V Parametric Ratings

Pinouts

CD4011BT (SBDIP), CDIP2-T14

TOP VIEW

A 1

B 2

J = AB 3

K = CD 4

C 5

D 6

14 V

13 H

12 G

11 M = GH

10 L = EF

9 E

8 F

Ordering Information

ORDERING

NUMBER

5962R9662101TCC

5962R9662101TXC

PART

NUMBER

CD4011BDTR

CD4011BKTR

TEMP.

RANGE

(

-55 to 125

J = AB

K = CD

CD4011BT (FLATPACK), CDFP3-F14

TOP VIEW

M = GH

L = EF

NOTE:

Minimum order quantity for -T is 150 units through

distribution, or 450 units direct.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

www.intersil.com or 407-727-9207

Intersil Corporation 1999

CD4011BKTR Related Products

	CD4011BKTR	5962R9662101TXC	5962R9662101TCC	CD4011BDTR
Description	4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14	4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14	4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14	4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14
Parts packaging code	DFP	DFP	DIP	DIP
package instruction	DFP, FL14,.3	DFP, FL14,.3	DIP, DIP14,.3	DIP, DIP14,.3
Contacts	14	14	14	14
Reach Compliance Code	not_compliant	unknown	unknown	not_compliant
series	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000
JESD-30 code	R-CDFP-F14	R-CDFP-F14	R-CDIP-T14	R-CDIP-T14
JESD-609 code	e0	e4	e4	e0
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	0.00064 A	0.00064 A	0.00064 A	0.00064 A
Number of functions	4	4	4	4
Number of entries	2	2	2	2
Number of terminals	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DFP	DIP	DIP
Encapsulate equivalent code	FL14,.3	FL14,.3	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	IN-LINE	IN-LINE
power supply	5/15 V	5/15 V	5/15 V	5/15 V
Prop。Delay @ Nom-Sup	338 ns	338 ns	338 ns	338 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO
Filter level	MIL-PRF-38535 Class T	MIL-PRF-38535 Class T	MIL-PRF-38535 Class T	MIL-PRF-38535 Class T
Maximum seat height	2.92 mm	2.92 mm	5.08 mm	5.08 mm
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	GOLD	GOLD	Tin/Lead (Sn/Pb)
Terminal form	FLAT	FLAT	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
width	6.285 mm	6.285 mm	7.62 mm	7.62 mm
Maker	Renesas Electronics Corporation	-	Renesas Electronics Corporation	Renesas Electronics Corporation
Base Number Matches	1	1	1	-

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