Single-chip with duration of 60, 75, 90, or 120 seconds.
Manual switch or microcontroller compatible
Playback can be edge- or level-activated
Directly cascadable for longer durations
Automatic power-down (push-button mode)
- Standby current 1 µA (typical)
Zero-power message storage
- Eliminates battery backup circuits
Fully addressable to handle multiple messages
100-year message retention (typical)
100,000 record cycles (typical)
On-chip clock source
Programmer support for play-only applications
Single +5 volt power supply
Available in die form, PDIP, SOIC and TSOP packaging
Packaged type: leaded and lead-free
Temperature = die (0°C to +50°C) and package (0°C to +70°C)
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•
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•
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-2-
ISD2560/75/90/120
3. BLOCK DIAGRAM
Internal Clock
XCLK
Timing
Sampling Clock
ANA IN
Amp
5-Pole Active
Antialiasing Filter
Decoders
Analog Transceivers
480K Cell
Nonvolatile
Multilevel Storage
Array
ANA OUT
MIC
MIC REF
AGC
Pre-
Amp
Automatic
Gain Control
(AGC)
Power Conditioning
5-Pole Active
Smoothing Filter
SP +
Mux
Amp
SP -
Address Buffers
Device Control
V
CCA
V
SSA
V
SSD
V
CCD
A0 A1 A2 A3
A4 A5 A6 A7 A8
A9
PD
OVF
P/R
CE
EOM
AUX IN
-3-
Publication Release Date: April 24, 2006
Revision 1.2
ISD2560/75/90/120
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
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ADI Reference Circuit
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