AM49DL640BG85IT datasheet, PDF

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AM49DL640BG85IT: DescriptionStacked Multi-Chip Package (MCP) Flash Memory and SRAM; Categorystorage storage; File Size558KB，62 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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AM49DL640BG85IT Overview

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

AM49DL640BG85IT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SPANSION
Parts packaging code	BGA
package instruction	8 X 11.60 MM, FBGA-73
Contacts	73
Reach Compliance Code	_compli
Maximum access time	85 ns
Other features	PSEUDO SRAM IS ORGANISED AS 2M X 16; FLASH IS ALSO CONFIGURABLE AS 8M X 8
JESD-30 code	R-PBGA-B73
JESD-609 code	e0
length	11.6 mm
memory density	67108864 bi
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+PSRAM
Humidity sensitivity level	3
Number of functions	1
Number of terminals	73
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA73,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.000005 A
Maximum slew rate	0.045 mA
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm
Base Number Matches	1

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Am49DL640BG

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number

26090

Revision

Amendment

Issue Date

March 8, 2002

P R E L I M I N A R Y

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

MCP Device Bus Operations . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V

... 10

Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V

..... 11

Figure 4. Erase Operation.............................................................. 28

Table 12. Am29DL640G Command Definitions .............................. 29

Flash Write Operation Status . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ................................................................. 30

Figure 5. Data# Polling Algorithm .................................................. 30

RY/BY#: Ready/Busy# ............................................................ 31

DQ6: Toggle Bit I .................................................................... 31

Figure 6. Toggle Bit Algorithm........................................................ 31

Flash Device Bus Operations . . . . . . . . . . . . . . . 12

Word/Byte Configuration ........................................................ 12

Requirements for Reading Array Data ................................... 12

Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation .......................................... 12

Autoselect Functions ........................................................... 12

Simultaneous Read/Write Operations with Zero Latency ....... 12

Standby Mode ........................................................................ 13

Automatic Sleep Mode ........................................................... 13

RESET#: Hardware Reset Pin ............................................... 13

Output Disable Mode .............................................................. 13

Table 3. Am29DL640G Sector Architecture ....................................14

Table 4. Bank Address ....................................................................17

Table 5. SecSi Sector Addresses ...............................................17

DQ2: Toggle Bit II ................................................................... 32

Reading Toggle Bits DQ6/DQ2 ............................................... 32

DQ5: Exceeded Timing Limits ................................................ 32

DQ3: Sector Erase Timer ....................................................... 32

Table 13. Write Operation Status ................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 7. Maximum Negative Overshoot Waveform ...................... 34

Figure 8. Maximum Positive Overshoot Waveform........................ 34

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 35

CMOS Compatible .................................................................. 35

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 37

Figure 10. Typical I

CC1

vs. Frequency ............................................ 37

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 11. Test Setup.................................................................... 38

Figure 12. Input Waveforms and Measurement Levels ................. 38

Sector/Sector Block Protection and Unprotection .................. 18

Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................18

pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 39

CE#s Timing ........................................................................... 39

Figure 13. Timing Diagram for Alternating

Between Pseudo SRAM to Flash................................................... 39

Write Protect (WP#) ................................................................ 19

Table 7. WP#/ACC Modes ..............................................................19

Read-Only Operations ........................................................... 40

Figure 14. Read Operation Timings ............................................... 40

Temporary Sector Unprotect .................................................. 19

Figure 1. Temporary Sector Unprotect Operation........................... 19

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 20

Hardware Reset (RESET#) .................................................... 41

Figure 15. Reset Timings ............................................................... 41

Word/Byte Configuration (CIOf) .............................................. 42

Figure 16. CIOf Timings for Read Operations................................ 42

Figure 17. CIOf Timings for Write Operations................................ 42

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 21

Hardware Data Protection ...................................................... 21

Low V

Write Inhibit ........................................................... 21

Write Pulse “Glitch” Protection ............................................ 22

Logical Inhibit ...................................................................... 22

Power-Up Write Inhibit ......................................................... 22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 8. CFI Query Identification String .......................................... 22

System Interface String................................................................... 23

Table 10. Device Geometry Definition ............................................ 23

Table 11. Primary Vendor-Specific Extended Query ...................... 24

Erase and Program Operations .............................................. 43

Figure 18. Program Operation Timings..........................................

Figure 19. Accelerated Program Timing Diagram..........................

Figure 20. Chip/Sector Erase Operation Timings ..........................

Figure 21. Back-to-back Read/Write Cycle Timings ......................

Figure 22. Data# Polling Timings (During Embedded Algorithms).

Figure 23. Toggle Bit Timings (During Embedded Algorithms)......

Figure 24. DQ2 vs. DQ6.................................................................

Temporary Sector Unprotect .................................................. 48

Figure 25. Temporary Sector Unprotect Timing Diagram .............. 48

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................................. 49

Flash Command Definitions . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................ 25

Reset Command ..................................................................... 25

Autoselect Command Sequence ............................................ 25

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 25

Byte/Word Program Command Sequence ............................. 26

Unlock Bypass Command Sequence .................................. 26

Figure 3. Program Operation .......................................................... 27

Alternate CE#f Controlled Erase and Program Operations .... 50

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)

Operation Timings.......................................................................... 51

Read Cycle ............................................................................. 52

Figure 28. Psuedo SRAM Read Cycle........................................... 52

Figure 29. Page Read Timing ........................................................ 53

Write Cycle ............................................................................. 54

Figure 30. Pseudo SRAM Write Cycle—WE# Control ................... 54

Figure 31. Pseudo SRAM Write Cycle—CE1#s Control ................ 55

Figure 32. Pseudo SRAM Write Cycle—

UB#s and LB#s Control.................................................................. 56

Chip Erase Command Sequence ........................................... 27

Sector Erase Command Sequence ........................................ 27

Erase Suspend/Erase Resume Commands ........................... 28

Flash Erase And Programming Performance . . 57

March 8, 2002

Am49DL640BG

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