BU-61843F3-582Y datasheet, PDF

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BU-61843F3-582Y: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP72, 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72; CategoryThe embedded processor and controller Microcontrollers and processors; File Size701KB，60 Pages; ManufacturerData Device Corporation

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BU-61843F3-582Y Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP72, 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72

BU-61843F3-582Y Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Data Device Corporation
Parts packaging code	QFP
package instruction	QFF,
Contacts	72
Reach Compliance Code	compliant
Address bus width	16
boundary scan	NO
maximum clock frequency	20 MHz
letter of agreement	MIL-STD-1553A; MIL-STD-1553B; MIL-STD-1760; MCAIR; STANAG-3838
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	S-CQFP-F72
JESD-609 code	e0
length	25.4 mm
low power mode	NO
Number of serial I/Os	2
Number of terminals	72
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	3.94 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	25.4 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

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BU-6174X/6184X/6186X

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ENHANCED MINIATURE ADVANCED

COMMUNICATIONS ENGINE

FEATURES

•

Fully Integrated 1553A/B Notice 2,

McAir, STANAG 3838 Interface Terminal

•

Compatible with Mini-ACE (Plus)

and ACE Generations

•

Choice of :

RT or BC/RT/MT In Same Footprint

- RT or BC/RT/MT with 4K RAM

- BC/RT/MT with 64K RAM, and RAM

parity

•

Choice of 5V or 3.3V Logic

•

5V Transceiver with 1760 and McAir

Compatible Options

•

Comprehensive Built-In Self-Test

DESCRIPTION

The Enhanced Miniature Advanced Communications Engine

(Enhanced Mini-ACE) family of MIL-STD-1553 terminals provide com-

plete interfaces between a host processor and a 1553 bus, and integrate

dual transceiver, protocol logic, and 4K words or 64K words of RAM.

These terminals are nearly 100% footprint and software compatible

with the previous generation Mini-ACE (Plus) terminals, and are soft-

ware compatible with the older ACE series.

They are powered by a choice of 5V or 3.3V logic. Multiprotocol sup-

port of MIL-STD-1553A/B and STANAG 3838, including versions

incorporating McAir compatible transmitters, is provided. There is a

choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT versions with

64K words of RAM include built-in RAM parity checking.

BC features include a built-in message sequence control engine, with

a set of 20 instructions. This provides an autonomous means of

implementing multi-frame message scheduling, message retry

schemes, data double buffering, asynchronous message insertion,

and reporting to the host CPU. The Enhanced Mini-ACE incorporates

a fully autonomous built-in self-test, which provides comprehensive

testing of the internal protocol logic and/or RAM.

The RT offers the same choices of subaddress buffering as the ACE

and Mini-ACE (Plus), along with a global circular buffering option,

50% rollover interrupt for circular buffers, an interrupt status queue,

and an "Auto-boot" option to support MIL-STD-1760.

These terminals provide the same flexibility in host interface configu-

rations as the ACE/Mini-ACE, along with a reduction in the host

processor's worst case holdoff time.

Data Device Corporation

105 Wilbur Place

Bohemia, New York 11716

631-567-5600 Fax: 631-567-7358

www.ddc-web.com

•

Flexible Processor/Memory Interface,

with Reduced Host Wait Time

•

Choice of 10, 12, 16, or 20 MHz Clock

•

Highly Autonomous BC with

Built-In Message Sequence Control:

- Frame Scheduling

- Branching

- Asynchronous Message Insertion

- General Purpose Queue

- User-defined Interrupts

•

Advanced RT Functions

- Global Circular Buffering

- Interrupt Status Queue

- 50% Circular Buffer Rollover

Interrupts

•

Selective Message Monitor

- Selection by Address, T/R Bit,

Subaddress

- Command and Data Stacks

- 50% and 100% Stack Rollover

Interrupts

FOR MORE INFORMATION CONTACT:

Technical Support:

1-800-DDC-5757 ext. 7234

2000 Data Device Corporation

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