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5962R9663601V9A

Description
4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, UUC15, DIE-15
Categorylogic    logic   
File Size74KB,7 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

5962R9663601V9A Overview

4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, UUC15, DIE-15

5962R9663601V9A Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?incompatible
Parts packaging codeDIE
package instructionDIE, DIE OR CHIP
Contacts15
Reach Compliance Codecompliant
series4000/14000/40000
JESD-30 codeR-XUUC-N15
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
Number of functions6
Number of entries1
Number of terminals15
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialUNSPECIFIED
encapsulated codeDIE
Encapsulate equivalent codeDIE OR CHIP
Package shapeRECTANGULAR
Package formUNCASED CHIP
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5/15 V
Prop。Delay @ Nom-Sup162 ns
propagation delay (tpd)162 ns
Certification statusNot Qualified
Schmitt triggerNO
Filter levelMIL-PRF-38535 Class V
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal locationUPPER
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose100k Rad(Si) V
Base Number Matches1
CD4049UBMS
Data Sheet
December 1992
File Number 3315
CMOS Hex Buffer/Converter
The CD4049UBMS is an inverting hex buffer and features
logic level conversion using only one supply (voltage (VCC).
The input signal high level (VIH) can exceed the VCC supply
voltage when this device is used for logic level conversions.
This device is intended for use as CMOS to DTL/TTL
converters and can drive directly two DTL/TTL loads. (VCC
= 5V, VOL
0.4V, and IOL
3.3mA.
The CD4049UBMS is designated as replacement for
CD4009UB. Because the CD4049UBMS requires only one
power supply, it is preferred over the CD4009UB and
CD4010B and should be used in place of the CD4009UB in
all inverter, current driver, or logic level conversion applica-
tions. In these applications the CD4049UBMS is pin compat-
ible with the CD4009UB, and can be substituted for this
device in existing as well as in new designs. Terminal No. 16
is not connected internally on the CD4049UBMS, therefore,
connection to this terminal is of no consequence to circuit
operation. For applications not requiring high sink current or
voltage conversion, the CD4069UB Hex Inverter is recom-
mended.
The CD4049UBMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4S
H1E
H3X
Features
• High Voltage Type (20V Rating)
• Inverting Type
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• 5V, 10V and 15V Parametric Ratings
Applications
• CMOS to DTL/TTL Hex Converter
• CMOS Current “Sink” or “Source” Driver
• CMOS High-to-Low Logic Level Converter
Pinout
CD4049UBMS
TOP VIEW
VCC
G=A
A
H=B
B
I=C
C
VSS
1
2
3
4
5
6
7
8
16 NC
15 L = F
14 F
13 NC
12 K = E
11 E
10 J = D
9 D
Functional Diagram
A
3
2
G=A
Schematic
VCC
B
5
4
H=B
C
7
6
I=C
IN
P
R
OUT
N
D
VCC
VSS
NC = 13
NC = 16
1
8
E
9
10
J=D
11
12
K=E
VSS
F
14
15
L=F
FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

5962R9663601V9A Related Products

5962R9663601V9A 5962R9663602VXC 5962R9663601VEC 5962R9663601VXC
Description 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, UUC15, DIE-15 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP16, CERAMIC, DFP-16 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDIP16, CERAMIC, DIP-16 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP16, CERAMIC, DFP-16
Parts packaging code DIE DFP DIP DFP
package instruction DIE, DIE OR CHIP DFP, FL16,.3 DIP, DIP16,.3 DFP, FL16,.3
Contacts 15 16 16 16
Reach Compliance Code compliant compliant compli compliant
series 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 code R-XUUC-N15 R-CDFP-F16 R-CDIP-T16 R-CDFP-F16
JESD-609 code e0 e4 e4 e4
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type INVERTER INVERTER INVERTER INVERTER
Number of functions 6 6 6 6
Number of entries 1 1 1 1
Number of terminals 15 16 16 16
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C
Package body material UNSPECIFIED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code DIE DFP DIP DFP
Encapsulate equivalent code DIE OR CHIP FL16,.3 DIP16,.3 FL16,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form UNCASED CHIP FLATPACK IN-LINE FLATPACK
power supply 5/15 V 5/15 V 5/15 V 5/15 V
propagation delay (tpd) 162 ns 162 ns 162 ns 162 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Schmitt trigger NO NO NO NO
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
Maximum supply voltage (Vsup) 18 V 18 V 18 V 18 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V
surface mount YES YES NO YES
technology CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY
Terminal surface TIN LEAD GOLD GOLD GOLD
Terminal form NO LEAD FLAT THROUGH-HOLE FLAT
Terminal location UPPER DUAL DUAL DUAL
total dose 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
Base Number Matches 1 1 1 1
Prop。Delay @ Nom-Sup 162 ns 162 ns - 162 ns
MaximumI(ol) - 0.0033 A 0.0033 A 0.0033 A
Terminal pitch - 1.27 mm 2.54 mm 1.27 mm

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