5962R9663601VEC datasheet, PDF

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5962R9663601VEC: Description4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDIP16, CERAMIC, DIP-16; Categorylogic logic; File Size74KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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5962R9663601VEC Overview

4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDIP16, CERAMIC, DIP-16

5962R9663601VEC Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	compli
Other features	RADIATION HARDENED; WITH EXTENDED INPUT VOLTAGE; IOL = 2.4MA @ VOL = 0.4V; IOH = 1.55MA @ VOH = 2.5V
series	4000/14000/40000
JESD-30 code	R-CDIP-T16
JESD-609 code	e4
length	19.05 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	INVERTER
MaximumI(ol)	0.0033 A
Number of functions	6
Number of entries	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5/15 V
Prop。Delay @ Nom-Su	162 ns
propagation delay (tpd)	162 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	MIL-PRF-38535 Class V
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
width	7.62 mm
Base Number Matches	1

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CD4049UBMS

Data Sheet

December 1992

File Number 3315

CMOS Hex Buffer/Converter

The CD4049UBMS is an inverting hex buffer and features

logic level conversion using only one supply (voltage (VCC).

The input signal high level (VIH) can exceed the VCC supply

voltage when this device is used for logic level conversions.

This device is intended for use as CMOS to DTL/TTL

converters and can drive directly two DTL/TTL loads. (VCC

= 5V, VOL

≤

0.4V, and IOL

≥

3.3mA.

The CD4049UBMS is designated as replacement for

CD4009UB. Because the CD4049UBMS requires only one

power supply, it is preferred over the CD4009UB and

CD4010B and should be used in place of the CD4009UB in

all inverter, current driver, or logic level conversion applica-

tions. In these applications the CD4049UBMS is pin compat-

ible with the CD4009UB, and can be substituted for this

device in existing as well as in new designs. Terminal No. 16

is not connected internally on the CD4049UBMS, therefore,

connection to this terminal is of no consequence to circuit

operation. For applications not requiring high sink current or

voltage conversion, the CD4069UB Hex Inverter is recom-

mended.

The CD4049UBMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4S

H1E

H3X

Features

• High Voltage Type (20V Rating)

• Inverting Type

• High Sink Current for Driving 2 TTL Loads

• High-to-Low Level Logic Conversion

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• 5V, 10V and 15V Parametric Ratings

Applications

• CMOS to DTL/TTL Hex Converter

• CMOS Current “Sink” or “Source” Driver

• CMOS High-to-Low Logic Level Converter

Pinout

CD4049UBMS

TOP VIEW

VCC

G=A

H=B

I=C

VSS

16 NC

15 L = F

14 F

13 NC

12 K = E

11 E

10 J = D

9 D

Functional Diagram

G=A

Schematic

VCC

H=B

I=C

OUT

VCC

VSS

NC = 13

NC = 16

J=D

K=E

VSS

L=F

FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

5962R9663601VEC Related Products

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Description	4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDIP16, CERAMIC, DIP-16	4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP16, CERAMIC, DFP-16	4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP16, CERAMIC, DFP-16	4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, UUC15, DIE-15
Parts packaging code	DIP	DFP	DFP	DIE
package instruction	DIP, DIP16,.3	DFP, FL16,.3	DFP, FL16,.3	DIE, DIE OR CHIP
Contacts	16	16	16	15
Reach Compliance Code	compli	compliant	compliant	compliant
series	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000
JESD-30 code	R-CDIP-T16	R-CDFP-F16	R-CDFP-F16	R-XUUC-N15
JESD-609 code	e4	e4	e4	e0
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	INVERTER	INVERTER	INVERTER	INVERTER
Number of functions	6	6	6	6
Number of entries	1	1	1	1
Number of terminals	16	16	16	15
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED
encapsulated code	DIP	DFP	DFP	DIE
Encapsulate equivalent code	DIP16,.3	FL16,.3	FL16,.3	DIE OR CHIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK	FLATPACK	UNCASED CHIP
power supply	5/15 V	5/15 V	5/15 V	5/15 V
propagation delay (tpd)	162 ns	162 ns	162 ns	162 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	18 V	18 V	18 V	18 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	GOLD	GOLD	GOLD	TIN LEAD
Terminal form	THROUGH-HOLE	FLAT	FLAT	NO LEAD
Terminal location	DUAL	DUAL	DUAL	UPPER
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
Base Number Matches	1	1	1	1
MaximumI(ol)	0.0033 A	0.0033 A	0.0033 A	-
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	-
Prop。Delay @ Nom-Sup	-	162 ns	162 ns	162 ns

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