Hitachi 16-Bit Single-chip Microcomputer
H8S/2357 Series,
H8S/2357
H8S/2352
H8S/2390
H8S/2392
H8S/2394
H8S/2357F-ZTAT
Hardware Manual
TM
ADE-602-146B
Rev. 3.0
11/10/00
Hitachi, Ltd.
Cautions
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have received the latest product standards or specifications before final design, purchase or
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However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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semiconductor products.
Preface
The H8S/2357 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*
1
), PROM (ZTAT™*
2
), and mask ROM versions
are available (H8S/2357 only), providing a quick and flexible response to conditions from ramp-
up through full-scale volume production, even for applications with frequently changing
specifications. A ROMless version, the H8S/2352, H8S/2390, H8S/2392 and H8S/2394 are also
available.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D
converter, D/A converter, and I/O ports.
In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided,
enabling high-speed data transfer without CPU intervention.
Use of the H8S/2357 Series enables easy implementation of compact, high-performance systems
capable of processing large volumes of data.
This manual describes the hardware of the H8S/2357 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Notes: 1. F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.
2. ZTAT is a trademark of Hitachi, Ltd.
Main Revisions and Additions in this Edition
Page
All pages of
this manual
Item
Revisions (See Manual for Details)
Amendments due to introduction of the H8S/2390, H8S/2392, H8S/2394, and
H8S/2398
Note added where needed
FWE pin in F-ZTAT version becomes
WDTOVF
pin in ZTAT version, mask ROM
version, or H8S/2532, and becomes V
CL
pin in H8S/2390, H8S/2392, or
H8S/2394.
Note on manual reset amended
Manual reset is only supported in the H8S/2357 ZTAT version.
SCI reception complete interrupt amended to SCI reception data full interrupt
3
1.1 Overview
Table 1-1 Overview
Memory description amended
5
1.1 Overview
Table 1-1 Overview
Product lineup description amended
6
1.2 Block Diagram
Figure 1-1 Block Diagram
Note 1 amended
9
1.3.1 Pin Arrangement
Figure 1-4 H8S/2394, H8S/2392, H8S/2390 Pin Arrangement (FP-120: Top View)
Added
9
1.3.1 Pin Arrangement
Figure 1-5 H8S/2394, H8S/2392, H8S/2390 Pin Arrangement (FP-128: Top View)
Added
12
1.3.2 Pin Functions in Each
Operating Mode
Table 1-2 Pin Functions in Each Operating Mode
Pin names of modes 5 to 7 for pins 65 to 69 of TFP-120 amended. V
CL
added to
pin names of modes 4 and 5 for pin 72 of TFP-120.
Table 1-3 Pin Functions
Internal voltage step-down drop pin added
15
1.3.3 Pin Functions
All pages of
section 2
68
3.1.2 Operating Mode
Selection (ZTAT, Mask ROM,
and ROMless Versions)
3.5 Memory Map in Each
Operating Mode
Note on TAS instruction added
Table 3-2 Operating Mode Selection (ZTAT, Mask ROM, and ROMless Versions)
Note amended
Figure 3-2 Memory Map in Each Operating Mode (H8S/2390)
Figure 3-3 Memory Map in Each Operating Mode (H8S/2352 and H8S/2392)
Figure 3-4 Memory Map in Each Operating Mode (H8S/2394)
Added
79-81
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