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M5M5V416BWG-70HI

Description
256K X 16 STANDARD SRAM, 70 ns, PBGA48
Categorystorage    storage   
File Size95KB,10 Pages
ManufacturerMitsubishi
Websitehttp://www.mitsubishielectric.com/semiconductors/
Download Datasheet Parametric View All

M5M5V416BWG-70HI Overview

256K X 16 STANDARD SRAM, 70 ns, PBGA48

M5M5V416BWG-70HI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMitsubishi
Parts packaging codeBGA
package instructionTFBGA, BGA48,6X8,30
Contacts48
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PBGA-B48
JESD-609 codee0
length8.5 mm
memory density4194304 bi
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals48
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA48,6X8,30
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3/3.3 V
Certification statusNot Qualified
Maximum seat height1.06 mm
Minimum standby current2 V
Maximum slew rate0.05 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width7 mm
revision-W03, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BWG
DESCRIPTION
The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs
organized as 262,144-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V416B is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V416BWG is packaged in a CSP (chip scale package),
with the outline of 7mm x 8.5mm, ball matrix of 6 x 8 (48pin) and
ball pitch of 0.75mm. It giv es the best solution f or a compaction
of mounting area as well as f lexibility of wiring pattern of printed
circuit boards.
From the point of operating temperature, the f amily is div ided
into three v ersions; "Standard", "W-v ersion", and "I-v ersion".
Version,
Operating
temperature
Part name
M5M5V416BWG -70L
M5M5V416BWG -85L
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
FEATURES
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage =2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S1, S2, BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 48pin 7mm x 8.5mm CSP
Stand-by c urrent Icc
(PD)
, Vcc=3.0V
Activ e
current
Ratings (max.)
Icc1
25°C 40°C 70°C 85°C (3.0V, ty p.)
---
---
20µA
---
Power
Supply
Access time
ty pical *
25°C
---
40°C
---
max.
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
Standard
0 ~ +70°C
M5M5V416BWG -10L
M5M5V416BWG -70H
M5M5V416BWG -85H
M5M5V416BWG -10H
M5M5V416BWG -70LW
M5M5V416BWG -85LW
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
0.3µA 1µA
1µA
3µA
10µA
---
---
---
---
---
20µA 40µA
40mA
(10MHz)
5mA
(1MHz)
W-
v ersion
M5M5V416BWG -10LW
M5M5V416BWG -85HW
M5M5V416BWG -10HW
M5M5V416WG -70LI
M5M5V416BWG -85LI
-20 ~ +85°C
M5M5V416BWG -70HW
2.7 ~ 3.6V
0.3µA 1µA
---
---
1µA
---
3µA
---
10µA 20µA
20µA 40µA
I-
v ersion
2.7 ~ 3.6V
M5M5V416BWG -10LI
M5M5V416BWG -85HI
M5M5V416BWG -10HI
-40 ~ +85°C
M5M5V416BWG -70HI
2.7 ~ 3.6V
0.3µA 1µA
1µA
3µA
10µA 20µA
PIN CONFIGURATION
(TOP VIEW)
A
B
C
D
E
F
G
Outline:
48FHA
NC: No Connection
H
1
BC1
* "ty pical" parameter is sampled, not 100% tested.
2
OE
3
A0
4
A1
5
A2
6
S2
Pin
DQ9
BC2
A3
A4
S1
DQ1
Function
Address input
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
Ground supply
A0 ~ A17
DQ1 ~ DQ16
DQ10
DQ11
A5
A6
DQ2
DQ3
S1
GND
DQ12
A17
A7
DQ4
VCC
S2
W
OE
BC1
BC2
Vcc
GND
VCC
DQ13
GND
A16
DQ5
GND
DQ15
DQ14
A14
A15
DQ6
DQ7
DQ16
N.C.
A12
A13
W
DQ8
N.C.
A8
A9
A10
A11
N.C.
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