5962-9460802MXC datasheet, PDF

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5962-9460802MXC: DescriptionMultiplier Accumulator/Summer, 12-Bit, CMOS, CPGA84; CategoryThe embedded processor and controller Microcontrollers and processors; File Size280KB，10 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

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5962-9460802MXC Overview

Multiplier Accumulator/Summer, 12-Bit, CMOS, CPGA84

5962-9460802MXC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	PGA,
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	2 X 12 BIT DATA INPUT BUS; PIPELINED 26-BIT OUT SUMMER; SELECTABLE CONFIGURATION FOR FILTERING APPL
boundary scan	NO
maximum clock frequency	28.6 MHz
External data bus width	12
JESD-30 code	S-CPGA-P84
JESD-609 code	e4
low power mode	NO
Humidity sensitivity level	3
Number of terminals	84
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output data bus width	26
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	PIN/PEG
Terminal location	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER
Base Number Matches	1

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5962-9460802MXC Related Products

	5962-9460802MXC	5962-9460801MXC	5962-9460801MXA	5962-9460802MXA
Description	Multiplier Accumulator/Summer, 12-Bit, CMOS, CPGA84	Multiplier Accumulator/Summer, 12-Bit, CMOS, CPGA84	Multiplier Accumulator/Summer, 12-Bit, CMOS, CPGA84	Multiplier Accumulator/Summer, 12-Bit, CMOS, CPGA84
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
package instruction	PGA,	PGA,	PGA,	PGA,
Reach Compliance Code	unknown	unknow	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Other features	2 X 12 BIT DATA INPUT BUS; PIPELINED 26-BIT OUT SUMMER; SELECTABLE CONFIGURATION FOR FILTERING APPL	2 X 12 BIT DATA INPUT BUS; PIPELINED 26-BIT OUT SUMMER; SELECTABLE CONFIGURATION FOR FILTERING APPL	2 X 12 BIT DATA INPUT BUS; PIPELINED 26-BIT OUT SUMMER; SELECTABLE CONFIGURATION FOR FILTERING APPL	2 X 12 BIT DATA INPUT BUS; PIPELINED 26-BIT OUT SUMMER; SELECTABLE CONFIGURATION FOR FILTERING APPL
boundary scan	NO	NO	NO	NO
maximum clock frequency	28.6 MHz	25 MHz	25 MHz	28.6 MHz
External data bus width	12	12	12	12
JESD-30 code	S-CPGA-P84	S-CPGA-P84	S-CPGA-P84	S-CPGA-P84
JESD-609 code	e4	e4	e0	e0
low power mode	NO	NO	NO	NO
Humidity sensitivity level	3	3	3	3
Number of terminals	84	84	84	84
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Output data bus width	26	26	26	26
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA	PGA	PGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	GOLD	GOLD	TIN LEAD	TIN LEAD
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER
Base Number Matches	1	1	1	1

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