DS2153Q+ datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> DS2153Q+

DS2153Q+: DescriptionFramer, CMOS, PQCC44, 0.652 INCH, ROHS COMPLIANT, PLASTIC, LCC-44; CategoryWireless rf/communication Telecom circuit; File Size796KB，62 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

Download Datasheet Parametric Compare View All

DS2153Q+ Overview

Framer, CMOS, PQCC44, 0.652 INCH, ROHS COMPLIANT, PLASTIC, LCC-44

DS2153Q+ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	LCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	compli
Carrier type	CEPT PCM-30/E-1
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
length	16.585 mm
Number of functions	1
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	FRAMER
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	16.585 mm
Base Number Matches	1

Preview

Download Datasheet

View All

DS2153Q

E1 Single-Chip Transceiver

www.maxim-ic.com

FEATURES

Complete E1 (CEPT) PCM-30/ISDN-PRI

Transceiver Functionality

On-Board Line Interface for Clock/Data

Recovery and Waveshaping

32-Bit or 128-Bit Jitter Attenuator

Generates Line Build-Outs for Both 120Ω

and 75Ω Lines

Frames to FAS, CAS, and CRC4 Formats

Dual On-Board Two-Frame Elastic Store Slip

Buffers That can Connect to Backplanes Up

to 8.192MHz

8-Bit Parallel Control Port That can be Used

on Either Multiplexed or Nonmultiplexed

Buses

Extracts and Inserts CAS Signaling

Detects and Generates Remote and AIS

Alarms

Programmable Output Clocks for Fractional

E1, H0, and H12 Applications

Fully Independent Transmit and Receive

Functionality

Full Access to Both Si and Sa Bits

Three Separate Loopbacks for Testing

Large Counters for Bipolar and Code

Violations, CRC4 Codeword Errors, FAS

Errors, and E Bits

Pin Compatible with DS2151Q T1 Single-

Chip Transceiver

5V Supply; Low-Power CMOS

PIN CONFIGURATION

FUNCTIONAL BLOCKS

LONG & SHORT

HAUL LINE

INTERFACE

FRAMER

PARALLEL CONTROL

PORT

Dallas

DS2153Q

T1SCT

ACTUAL SIZE OF 44-PIN PLCC

TCHCLK

RD(DS)

AD7

AD6

AD5

AD4

AD3

AD2

AD1

ALE(AS)

(R/W)

RLINK

RLCLK

DVSS

RCLK

RCHCLK

RSER

RSYNC

RLOS/LOTC

SYSCLK

AD0

ELASTIC

STORES

DS2153Q

TSER

TCLK

DVDD

TSYNC

TLINK

TLCLK

TCHBLK

TRING

TVDD

TVSS

TTIP

RTIP

INT1

XTAL1

RCHBLK

RRING

ORDERING INFORMATION

PART

DS2153Q

DS2153Q+

DS2153QN

DS2153QN+

TEMP

RANGE

0°C to +70°C

-40°C to +85°C

PIN-

PACKAGE

44 PLCC

PLCC

Denotes lead-free/RoHS-compliant package.

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

1 of 60

XTAL2

ACLKI

RVDD

RVSS

INT2

BTS

REV: 01106

DS2153Q

TABLE OF CONTENTS

DETAILED DESCRIPTION....................................................................................................4

1.1

1.2

2.1

NTRODUCTION

................................................................................................................................ 4

EADER

’

OTE

.............................................................................................................................. 4

DS2153Q R

EGISTER

............................................................................................................... 8

PIN DESCRIPTION................................................................................................................6

PARALLEL PORT .................................................................................................................9

CONTROL AND TEST REGISTERS...................................................................................10

4.1

4.2

4.3

4.4

4.5

OCAL

OOPBACK

......................................................................................................................... 17

EMOTE

OOPBACK

...................................................................................................................... 17

RAMER

OOPBACK

...................................................................................................................... 17

UTOMATIC

LARM

ENERATION

................................................................................................... 17

OWER

-U

EQUENCE

................................................................................................................. 17

CRC4 S

YNC

OUNTER

................................................................................................................. 20

BPV

ODE

IOLATION

OUNTER

............................................................................................. 26

CRC4 E

RROR

OUNTER

............................................................................................................... 27

E-B

OUNTER

............................................................................................................................ 27

FAS B

RROR

OUNTER

............................................................................................................ 28

STATUS AND INFORMATION REGISTERS ......................................................................18

5.1

6.1

6.2

6.3

6.4

ERROR COUNT REGISTERS.............................................................................................26

7 SA DATA LINK CONTROL AND OPERATION ..................................................................29

8 SIGNALING OPERATION...................................................................................................30

9 TRANSMIT IDLE REGISTERS............................................................................................32

10 CLOCK BLOCKING REGISTERS....................................................................................33

11 ELASTIC STORES OPERATION.....................................................................................35

12 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................36

13 LINE INTERFACE FUNCTIONS.......................................................................................39

13.1

13.2

13.3

ECEIVE

LOCK AND

ATA

ECOVERY

....................................................................................... 40

RANSMIT

AVESHAPING AND

INE

RIVING

.............................................................................. 41

ITTER

TTENUATOR

.................................................................................................................. 42

TIMING DIAGRAMS .........................................................................................................46

DC CHARACTERISTICS..................................................................................................52

AC CHARACTERISTICS..................................................................................................53

PACKAGE INFORMATION..............................................................................................60

44-P

PLCC (56-G4003-001).................................................................................................. 60

17.1

2 of 60

DS2153Q

LIST OF FIGURES

Figure 1-1. DS2153Q Block Diagram ......................................................................................................... 5

Figure 13-1. External Analog Connections............................................................................................... 43

Figure 13-2. Jitter Tolerance .................................................................................................................... 44

Figure 13-3. Transmit Waveform Template .............................................................................................. 44

Figure 13-4. Jitter Attenuation .................................................................................................................. 45

Figure 14-1. Receive Side Timing ............................................................................................................ 46

Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled) ............................................ 46

Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled ................................................. 47

Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled.................................................. 47

Figure 14-5. Transmit Side Timing ........................................................................................................... 48

Figure 14-6. Transmit Side Boundary Timing ........................................................................................... 48

Figure 14-7. G.802 Timing........................................................................................................................ 49

Figure 14-8. Synchronization Flowchart ................................................................................................... 50

Figure 14-9. Transmit Data Flow .............................................................................................................. 51

Figure 16-1. Intel Bus Read AC Timing.................................................................................................... 54

Figure 16-2. Intel Bus Write AC Timing .................................................................................................... 54

Figure 16-3. Motorola Bus AC Timing ...................................................................................................... 55

Figure 16-4. Receive Side AC Timing ...................................................................................................... 57

Figure 16-5. Transmit Side AC Timing ..................................................................................................... 59

LIST OF TABLES

Table 4-1. Sync/Resync Criteria............................................................................................................... 11

Table 5-1. Alarm Set and Clear Criteria ................................................................................................... 22

Table 13-1. Source of RCLK Upon RCL................................................................................................... 40

Table 13-2. LBO Select in LICR ............................................................................................................... 41

Table 13-3. Transformer Specifications.................................................................................................... 41

Table 13-4. Crystal Selection Guidelines ................................................................................................. 42

Table 15-1. Recommended DC Characteristics ....................................................................................... 52

Table 15-2. Capacitance .......................................................................................................................... 52

Table 15-3. DC Characteristics ................................................................................................................ 52

Table 16-1. AC Characteristics—Parallel Port ......................................................................................... 53

Table 16-2. AC Characteristics—Receive Side ........................................................................................ 56

Table 16-3. AC Characteristics—Transmit Side ....................................................................................... 58

3 of 60

DS2153Q

1 DETAILED DESCRIPTION

The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1

lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial

stream. The DS2153Q automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to 1.5km.

The device can generate the necessary G.703 waveshapes for both 75Ω and 120Ω cables. The on-board

jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data

paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It

is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a

set of 71 8-bit internal registers that the user can access to control the operation of the unit. Quick access

via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all the

latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011,

300 233, TBR 12 and TBR 13.

1.1 Introduction

The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of

the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing

pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency

differences between the recovered E1 data stream and an asynchronous backplane clock which is

provided at the SYSCLK input.

The transmit side of the DS2153Q is totally independent from the receive side in both the clock

requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1

transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation

mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP

and TRING pins via a coupling transformer.

1.2 Reader’s Note

This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit

time slots in E1 systems that are numbered 0 to 31. Time slot 0 is transmitted first and received first.

These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is

identical to channel 1, time slot 1 is identical to channel 2, and so on. Each time slot (or channel) is made

up of 8 bits numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB

and is transmitted last. Throughout this data sheet, the following abbreviations are used:

FAS

CAS

CRC4

CCS

E-bit

Frame Alignment Signal

Channel Associated Signaling

Multiframe

International Bits

Cyclical Redundancy Check

Common Channel Signaling

Additional bits

CRC4 Error bits

4 of 60

DS2153Q+ Related Products

	DS2153Q+	DS2153QN+
Description	Framer, CMOS, PQCC44, 0.652 INCH, ROHS COMPLIANT, PLASTIC, LCC-44	Framer, CMOS, PQCC44, 0.652 INCH, ROHS COMPLIANT, PLASTIC, LCC-44
Is it Rohs certified?	conform to	conform to
Parts packaging code	LCC	LCC
package instruction	QCCJ, LDCC44,.7SQ	QCCJ, LDCC44,.7SQ
Contacts	44	44
Reach Compliance Code	compli	compli
Carrier type	CEPT PCM-30/E-1	CEPT PCM-30/E-1
JESD-30 code	S-PQCC-J44	S-PQCC-J44
JESD-609 code	e3	e3
length	16.585 mm	16.585 mm
Number of functions	1	1
Number of terminals	44	44
Maximum operating temperature	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ	LDCC44,.7SQ
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	4.572 mm
Nominal supply voltage	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Telecom integrated circuit types	FRAMER	FRAMER
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	16.585 mm	16.585 mm
Base Number Matches	1	1

Recommended Resources

Vehicle network electronic control unit circuit diagram

MAX230 multi-channel data interface circuit

Solar charger circuit

Power circuit diagram

Line Voltage Sag Detector Circuit Diagram

Control the starting of DC motor according to the current principle

Earrings for girls majoring in science and engineering: ...; chenzhufly Talking

Circuit Design Talk 12: High frequencies like low inductive reactance, low frequencies like low (electrical) impedance - Let's talk about grounding again.: [font=Arial][size=2]The performance of a hybrid circuit depends on 1) the circuit itself and 2) the PCB design. No matter how good the circuit design is, it is difficult to achieve the predetermined d...; linda_xia Analog electronics

Several pins of vca820 and its simulation problems: [color=#222222][backcolor=rgb(238, 238, 238)][/backcolor][/color][color=rgb(34, 34, 34)][backcolor=rgb(238, 238, 238)][font=sans-serif][size=12px][table=98%] [tr][td]The simulated graphics are the mos...; 关耳008 Analog electronics

DIY navigation obstacle avoidance vehicle task division and rules and regulations: 1. Focused discussion and progress report will be held at around 2pm every Saturday. (You must be online unless there are special circumstances. If you cannot be online, please leave a message in the ...; missforever Microcontroller MCU

What is the function of the GMIIEN bit in the TMS570LS3137 MAC Control Register (MACCONTROL)?: What is the function of the GMIIEN bit in the TMS570LS3137 MAC Control Register (MACCONTROL)?...; yueyuanlong232 Microcontroller MCU

Comparison of two mainstream solutions at home and abroad, please give me some advice: [i=s]This post was last edited by paulhyde on 2014-9-15 08:57[/i]...; gemini338 Electronics Design Contest

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components