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813253BGLFT

Description
TSSOP-24, Reel
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size389KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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813253BGLFT Overview

TSSOP-24, Reel

813253BGLFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction4.40 X 7.85 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
Contacts24
Manufacturer packaging codePGG24
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Humidity sensitivity level1
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency340 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency136 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate130 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
FemtoClock
®
Jitter Attenuator & Multiplier
Frequency Translator w/LVPECL Outputs
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES APRIL 25, 2015
ICS813253
DATASHEET
General Description
The ICS813253 is a PLL based synchronous clock generator that is
optimized for Gigabit Ethernet and PCI Express™
clock jitter
attenuation and frequency translation. The device contains two
internal frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide reference
clock jitter attenuation. The second stage is a FemtoClock®
frequency multiplier that provides the low jitter, high frequency
Gigabit Ethernet or PCI Express™
output clock.
Pre-divider and output divider multiplication ratios are selected using
device selection control pins. The multiplication ratios are optimized
to support most common clock rates used in Gigabit Ethernet and
PCI-Express applications. The VCXO requires the use of an external,
inexpensive pullable crystal. The VCXO uses external passive loop
filter components which allows configuration of the PLL loop
bandwidth and damping characteristics.
Features
Three differential LVPECL output pairs
One differential input supports the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Accepts input frequencies from 19.6MHz to 136MHz, including:
25MHz, 62.5MHz, 100MHz and 125MHz input clocks
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode VCXO crystal
Outputs common Gigabit Ethernet or PCI Express clock rates
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
Absolute pull range: ±50ppm
FemtoClock frequency multiplier provides low jitter,
high frequency output
FemtoClock VCO range: 490MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.421ps (typical)
Full 3.3V supply, or mixed 3.3V core 2.5V output supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Use replacement devices 813N252CKI-02LF, 813N252BKI-04LF
LF
V
CCA
V
CC
V
CCO
nQ0
Q0
PSEL0
V
EE
PSEL1
XTAL_OUT
XTAL_IN
V
EE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
V
CCO
nQ2
Q2
nQ1
Q1
FSEL0
V
EE
FSEL1
nBYPASS
CLK
nCLK
Pin Assignment
ICS813253
24 Lead TSSOP
4.4mm x 7.85mm x 0.925mm
package body
G Package
Top View
XTAL_OUT
Block Diagram
LF
XTAL_IN
nBypass
Pullup
Q0
0
CLK
nCLK
PSEL0
PSEL1
FSEL0
FSEL1
OE
Pulldown
Pullup/Pulldown
Pre-Divider
1, 2.5,
4, 5
Phase
Detector
VCXO
FemtoClock
Frequency
Multiplier x25
1
Output
Divider
2, 4, 5, 25
nQ0
Q1
nQ1
Q2
Pullup
Pullup
Pullup
Pullup
Pullup
VCXO Jitter Attenuation PLL
nQ2
ICS813253 REVISION A MAY 9, 2014
1
©2014 Integrated Device Technology, Inc.
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