5962-8852505UX datasheet, PDF - EEWORLD Datasheet

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5962-8852505UX: DescriptionEEPROM, 32KX8, 250ns, Parallel, CMOS, CPGA28, CERAMIC, PGA-28; Categorystorage storage; File Size660KB，25 Pages; ManufacturerAtmel (Microchip)

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5962-8852505UX Overview

EEPROM, 32KX8, 250ns, Parallel, CMOS, CPGA28, CERAMIC, PGA-28

5962-8852505UX Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	PGA
package instruction	PGA,
Contacts	28
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	250 ns
Other features	AUTOMATIC WRITE
JESD-30 code	R-CPGA-P28
JESD-609 code	e0
length	16.51 mm
memory density	262144 bit
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	28
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	32KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programming voltage	5 V
Certification status	Not Qualified
Filter level	MIL-STD-883 Class C
Maximum seat height	4.4 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13.97 mm
Maximum write cycle time (tWC)	10 ms
Base Number Matches	1

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Features

•

Fast Read Access Time – 150 ns

•

Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes

– Internal Control Timer

Fast Write Cycle Times

– Page Write Cycle Time: 3 ms or 10 ms Maximum

– 1 to 64-byte Page Write Operation

Low Power Dissipation

– 50 mA Active Current

– 200 µA CMOS Standby Current

Hardware and Software Data Protection

DATA Polling for End of Write Detection

High Reliability CMOS Technology

– Endurance: 10

or 10

Cycles

– Data Retention: 10 Years

Single 5V

10% Supply

CMOS and TTL Compatible Inputs and Outputs

JEDEC Approved Byte-wide Pinout

Full Military and Industrial Temperature Ranges

Green (Pb/Halide-free) Packaging Option

•

256K (32K x 8)

Paged Parallel

EEPROM

AT28C256

•

1. Description

The AT28C256 is a high-performance electrically erasable and programmable read-

only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-

tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access

times to 150 ns with power dissipation of just 440 mW. When the device is deselected,

the CMOS standby current is less than 200 µA.

The AT28C256 is accessed like a Static RAM for the read or write cycle without the

need for external components. The device contains a 64-byte page register to allow

writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to

64 bytes of data are internally latched, freeing the address and data bus for other

operations. Following the initiation of a write cycle, the device will automatically write

the latched data using an internal control timer. The end of a write cycle can be

detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a

new access for a read or write can begin.

Atmel’s AT28C256 has additional features to ensure high quality and manufacturabil-

ity. The device utilizes internal error correction for extended endurance and improved

data retention characteristics. An optional software data protection mechanism is

available to guard against inadvertent writes. The device also includes an extra

64 bytes of EEPROM for device identification or tracking.

0006M–PEEPR–12/09

AT28C256

3. Block Diagram

4. Device Operation

4.1

Read

The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the address pins is asserted on the outputs.

The outputs are put in the high impedance state when either CE or OE is high. This dual-line

control gives designers flexibility in preventing bus contention in their system.

4.2

Byte Write

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write

cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Once a byte write has been started it will automati-

cally time itself to completion. Once a programming operation has been initiated and for the

duration of t

, a read operation will effectively be a polling operation.

4.3

Page Write

The page write operation of the AT28C256 allows 1 to 64 bytes of data to be written into the

device during a single internal programming period. A page write operation is initiated in the

same manner as a byte write; the first byte written can then be followed by 1 to 63 additional

bytes. Each successive byte must be written within 150 µs (t

BLC

) of the previous byte. If the t

BLC

limit is exceeded the AT28C256 will cease accepting data and commence the internal program-

ming operation. All bytes during a page write operation must reside on the same page as

defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page

write operation, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes

may be loaded in any order and may be altered within the same load period. Only bytes which

are specified for writing will be written; unnecessary cycling of other bytes within the page does

not occur.

4.4

DATA Polling

The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page

write cycle an attempted read of the last byte written will result in the complement of the written

data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all

outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write

cycle.

0006M–PEEPR–12/09

4.5

Toggle Bit

In addition to DATA Polling the AT28C256 provides another method for determining the end of a

write cycle. During the write operation, successive attempts to read data from the device will

result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-

gling and valid data will be read. Reading the toggle bit may begin at any time during the write

cycle.

4.6

Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system

power supply. Atmel has incorporated both hardware and software features that will protect the

memory against inadvertent writes.

4.6.1

Hardware Protection

Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a)

sense – if V

is below 3.8V (typical) the write function is inhibited; (b) V

power-on delay –

once V

has reached 3.8V the device will automatically time out 5 ms (typical) before allowing

a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles;

and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a

write cycle.

Software Data Protection

A software controlled data protection feature has been implemented on the AT28C256. When

enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature

may be enabled or disabled by the user; the AT28C256 is shipped from Atmel with SDP

disabled.

SDP is enabled by the host system issuing a series of three write commands; three specific

bytes of data are written to three specific addresses (refer to “Software Data Protection” algo-

rithm). After writing the 3-byte command sequence and after t

the entire AT28C256 will be

protected against inadvertent write operations. It should be noted, that once protected the host

may still perform a byte or page write to the AT28C256. This is done by preceding the data to be

written by the same 3-byte command sequence used to enable SDP.

Once set, SDP will remain active unless the disable command sequence is issued. Power transi-

tions do not disable SDP and SDP will protect the AT28C256 during power-up and power-down

conditions. All command sequences must conform to the page write timing specifications. The

data in the enable and disable command sequences is not written to the device and the memory

addresses used in the sequence may be written with data in either a byte or page write

operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will

start the internal write timers. No data will be written to the device; however, for the duration of

, read operations will effectively be polling operations.

4.6.2

4.7

Device Identification

An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-

ing A9 to 12V

0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be

written to or read from in the same manner as the regular memory array.

4.8

Optional Chip Erase Mode

The entire device can be erased using a 6-byte software code. Please see “Software Chip

Erase” application note for details.

AT28C256

0006M–PEEPR–12/09

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