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54AC273DMQB

Description
FF/Latch
Categorylogic    logic   
File Size158KB,8 Pages
Manufacturere2v technologies
Download Datasheet Parametric Compare View All

54AC273DMQB Overview

FF/Latch

54AC273DMQB Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codecompliant
Base Number Matches1
54AC273 Octal D Flip-Flop
54AC273
July 1998
54AC273
Octal D Flip-Flop
General Description
The ’273 has eight edge-triggered D-type flip-flops with indi-
vidual D inputs and Q outputs. The common buffered Clock
(CP) and Master Reset (MR) input load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
n
n
n
n
n
n
n
n
n
n
Ideal buffer for microprocessor or memory
Eight edge-triggered D flip-flops
Buffered common clock
Buffered, asynchronous master reset
See ’377 for clock enable version
See ’373 for transparent latch version
See ’374 for TRI-STATE
®
version
Outputs source/sink 24 mA
’ACT has TTL-compatible inputs
Standard Military Drawing (SMD)
— ’AC273: 5962-87756
Logic Symbols
IEEE/IEC
DS100288-1
DS100288-2
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100288
www.national.com
1
PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1
cmserv
Proof
1

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Reach Compliance Code compliant compliant compliant
Base Number Matches 1 1 1
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