M2S28D30ATP-10 datasheet, PDF - EEWORLD Datasheet

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M2S28D30ATP-10: Description128M Double Data Rate Synchronous DRAM; Categorystorage storage; File Size1MB，36 Pages; ManufacturerMitsubishi; Websitehttp://www.mitsubishielectric.com/semiconductors/

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M2S28D30ATP-10 Overview

128M Double Data Rate Synchronous DRAM

M2S28D30ATP-10 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Mitsubishi
Parts packaging code	TSOP2
package instruction	SOP, TSSOP66,.46
Contacts	66
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.8 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	125 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
JESD-609 code	e0
memory density	134217728 bi
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	66
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.02 A
Maximum slew rate	0.16 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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DDR SDRAM (Rev.0.1)

Jun,'00

Preliminary

MITSUBISHI LSIs

M2S28D20/ 30/ 40ATP

128M Double Data Rate Synchronous DRAM

PRELIMINARY

Some of contents are subject to change without notice.

DESCRIPTION

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit,

M2S28D30ATP is a 4-bank x 4194304-word x 8-bit,

M2S28D40ATP is a 4-bank x 2097152-word x 16-bit,

double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are

referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output

data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very

high speed data rate up to 133MHz, and are suitable for main memory in computer systems.

FEATURES

- Vdd=Vddq=2.5V+0.2V

- Double data rate architecture;

two data transfers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/received with data

- Differential clock inputs (CLK and /CLK)

- DLL aligns DQ and DQS transitions

with CLK transitions edges of DQS

- Commands entered on each positive CLK edge;

- data and data mask referenced to both edges of DQS

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Burst type- sequential / interleave (programmable)

- Auto precharge / All bank precharge controlled by A10

- 4096 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- SSTL_2 Interface

- 400-mil, 66-pin Thin Small Outline Package (TSOP II)

- FET switch control(/QFC) for x4/ x8

- JEDEC standard

MITSUBISHI ELECTRIC

M2S28D30ATP-10 Related Products

	M2S28D30ATP-10	M2V28D40ATP-10	M2V28D30ATP-10	M2V28D20ATP-10	M2S28D40ATP-10	M2S28D20ATP-10
Description	128M Double Data Rate Synchronous DRAM	128M Double Data Rate Synchronous DRAM	128M Double Data Rate Synchronous DRAM	128M Double Data Rate Synchronous DRAM	128M Double Data Rate Synchronous DRAM	128M Double Data Rate Synchronous DRAM

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