IF Modulator/Demodulator IC
Technical Data
HPMX-5002
Features
• Use with HPMX-5001
Up/Down Converter Chip
for DECT Telephone
Applications
• 2.7– 5.5 V Single Supply
Voltage
• >75 dB RSSI Range
• Internal Data Slicer
• On-chip LO Generation,
Including VCO, Prescalers
and Phase/ Frequency
Detector
• Flexible Chip Biasing,
Including Standby Mode
• Supports Reference Crystal
Frequencies of 9, 12, and 16
Times the DECT Bit Rate
(1.152 MHz)
• IF Input Frequency Range
up to 250 MHz
• TQFP-48 Surface Mount
Package
Plastic TQFP-48 Package
Description
The Hewlett-Packard HPMX-5002
IF Modulator/Demodulator
provides all of the active compo-
nents necessary for the demodula-
tion of a downconverted DECT
signal. Designed specifically for
DECT, the HPMX-5002 contains a
down-conversion mixer (to a 2nd
IF), limiting amplifier chain,
discriminator/data slicer, lock
detector, and RSSI circuits. The
LO2 generation is also included
on-chip, via a VCO, dividers, and
phase/frequency detector. The
divide ratios are programmable to
support reference frequencies of
either 9, 12, or 16 times the DECT
bit rate of 1.152 MHz allowing the
use of common, low cost crystals.
The LO2 VCO can also be utilized in
transmit mode by directly modulat-
ing the external VCO tank. An AGC
loop in the buffered VCO output
suppresses harmonics and reduces
signal level variability.
The HPMX-5002 is designed to meet
the size and power demands of
portable applications. Battery cell
count and cost are reduced due to
the 2.7 V minimum supply voltage.
The TQFP-48 package, combined
with the high level of integration,
means smaller footprints and fewer
components. Flexible chip biasing
takes full advantage of the power
savings inherent in time-duplexed
systems such as DECT.
5965-9106E
X
HPM3
943
5
643
0
– 50
2
019
Pin Configuration
48
1
37
36
HPMX–5002
9433
6435
12
13
019
25
24
Applications
• DECT, Unlicensed PCS and
ISM Band Handsets,
Basestations and Wireless
LANs
7-105
100 kΩ
4
100 kΩ
5
0.1
µ
3
6
2
7
1
8
100 kΩ
= connector
= terminal
DC post
0.01
µ
0.01
µ
0.01
µ
6 kΩ
1000 p
15
µH
3.9 p
22 p
3 to 10 p
0.01
µ
49.9
Ω
0.01
µ
0.01
µ
0.01
µ
1 kΩ
10
Ω
0.01
µ
0.01
µ
100 p
0.01
µ
1F1P1
10 p
2.7
µH
100 p
0.01
µ
0
Ω
3.9
µH
VSUB
DC1B
48
1
IFOP1
DMOD
DC1A
VCC2
VEE2
BGR
XLO
PLL
NC
NC
RX
37
36
NC
IF1
VEE1
VCC1
0
Ω
0.01
µ
10 p
10
Ω
0.01
µ
270 nH
0.01
µ
0.01
µ
270 nH
1p
0
Ω
1.2 k
Ω
3.9
µH
68 p
4.7 kΩ
22 p
DMODOP
BUF1
BUF2
TCNT
DATA
SLICER
R
S
S
I
0.01
µ
1p
100 nH
22 p
68 p
4.7 kΩ
IP1
IPDC
VEE5
VCC5
0.01
µ
0
Ω
1000 p
TCSET
DATOP
10 p
20 kΩ
1000 p
RSS1
LKFIL
LKDET
REF
49.9
Ω
8.2 p
0
Ω
0
Ω
8.2 p
220 nH
8.2 p 1000 p
20 kΩ
20 kΩ
1 kΩ
LOCK
DET
φ
Freq.
Det.
90/216
OSCOPB
OSCOP
9/12/16
CHARGE
PUMP
VCOADJ
VCOB
12
VCOA
VCC3
VCC4
VEE3
VEE4
D1V1
D1V2
D1V3
AGC
PFD
25
13
24
1 kΩ
1000 p
1000 p
NC
NC
51.1
Ω
0.01
µ
0
Ω
0.01
µ
0
Ω
3.9 p
120 n
10 kΩ
22 p
0.01
µ
10
Ω
6
5
4
0.01
µ
0.01
µ
0
Ω
0.01
µ
10
Ω
0.01
µ
1 kΩ
4400 p
330 p
0.01
µ
0.01
µ
4.7 kΩ
3.3 kΩ
1000 p
1
2
3
1 kΩ
0
Ω
0.01
µ
10 kΩ
Figure 1. HPMX-5002 Test Board Schematic Diagram.
7-106
HPMX-5002 Functional Block Diagram
IFIP1
IF1
IFOP1
DMOD
DMODOP
BUF1
BUF2
TCSET
IP1
DATA
SLICER
RSSI
DATAOP
RSSI
DIV2
OSCOP
90/216
OSCOPB
CHARGE
PUMP
φ
FREQ.
DET.
9/12/16
DIV1
LOCK
DET.
BIAS
CONTROL
REF
BGR
VCOADJ
VCOB
VCOA
DIV3
PFD
LKDET
PLL
RX
XLO
HPMX-5002 Absolute Maximum Ratings
[1]
Symbol
Parameter
V
CC
Supply Voltage
Voltage at any Pin
[4]
Power Dissipation
[2,3]
Junction Temperature
Storage Temperature
Units
V
V
mW
°C
°C
Min.
-0.2
-0.2
Max.
7.5
V
CC
+ 0.2
200
+110
+125
Thermal Resistance
[2]
:
θ
jc
= 80°C/W
Notes:
1. Operation of this device in excess
of any of these parameters may
cause permanent damage.
2. T
case
= 25°C
3. Derate at 10 mW/°C for T
case
> 90°C
4. Except CMOS logic inputs, see
Summary Characterization
Information Table.
P
diss
T
STG
-55
HPMX-5002 Guaranteed Electrical Specifications
Unless otherwise noted, all parameters are guaranteed under the following conditions: 2.7 V < V
CC
< 5.5 V.
Test results are based upon use of networks shown in test diagram (see Figure 1). f
in
= 110.592 MHz.
Typical values are for V
CCX
= 3.0 V, T
A
= 25°C.
Symbol
Parameters and Test Conditions
Units
Min.
Typ.
Max.
I
ccx
Total V
ccx
supply current
(PLL locked)
(PLL locked)
RX mode
PLL mode
TX “flywheel” mode
Standby mode
high current mode
low current mode
input matched to 50
Ω
mA
mA
mA
µA
µA
µA
dB
21
16
9
400
30
5
550
50
8
27
20
11.5
100
1000
100
GIF1
VDATOP
VDATOP
Charge pump current
Charge pump current
Mixer power gain from
IP1 to IF1, external load
impedance of 600
Ω
Data slicer output level
Data slicer output level
Logic ‘0’
Logic ‘1’
V
V
0.3
V
ccx
-0.3
7-107
HPMX-5002 Summary Characterization Information
Typical values measured on test board shown in Figure 1 at V
ccx
= 3.0 V, T
A
= 25°C,
f
in
= 110.592 MHz, f
LO2
= 103.68 MHz, unless otherwise noted.
Symbol
V
IH
V
IL
I
IH
I
IL
P
1 dB
I
IP3
NF
IF1
Z
inIP1
Parameters and Test Conditions
CMOS input high voltage (can be pulled up as high as V
cc
+7V)
CMOS input low voltage
CMOS input high current
CMOS input low current
Mode switching time
Mixer input 1 dB compression point
Mixer input IP3
Mixer SSB noise figure
(see test diagram Fig. 1)
Mixer input impedance
matched to 50
Ω
source
matched to 50
Ω
source
input matched to 50
Ω
source, 600
Ω
load at output
50 MHz < f
in
< 250 MHz
Units
V
V
µA
µA
µS
dBm
dBm
dB
Ω
dB
mV/dB
V
Typ.
≥
V
cc
-0.8
≤
1.0
<50
> - 50
<1
-23
-17
12
100
75
17
0.88
1.48
2.04
30
45
57
600
335
80:1
-142
<100
1.1
RSSI dynamic range
Note 1
(for signal input at IFIP1; RSSI output measured with 6 bit ADC)
RSSI voltage change
RSSI output voltage. V
ccx
= 3 V,
V
RSSI
is monotonic
Note 1
2 IF limiter input level:
- 90 dBm
-50 dBm
-20 dBm
Z
outRSSI
IF2f
3 dB
A
VIF2
Z
inIFIP1
V
outLO2
RSSI output impedance
IF2 limiter bandwidth
IF2 limiter voltage gain
IF2 limiter input impedance at pin IFIP1
Prior to limiting, Note 2
Note 2
kΩ
MHz
dB
Ω
mVp-p
LO2 output buffer differential amplitude >1.5 kΩ differential load,
(between OSCOP and OSCOPB)
f
vco
=103.68 MHz, V
CC
=3 V
Bit slicer time constant ratio
LO2 VCO output buffer noise floor
(@ 4 MHz offset)
PLL charge pump leakage current
TCSET =0 vs. TCSET = 1
tank circuit Q = 35 dBc/Hz
pA
Logic ‘0’ (unlocked)
mA
ILKDET
Lock detector current sink
Notes:
1: RSSI signal is monotonic over stated dynamic range, but not necessarily linear. Voltage change is
defined in the linear region of the transfer curve.
2: IF2 frequency in the range 1 MHz < f < 45 MHz, with 10 nF capacitors from DC1A and DC1B to
ground.
7-108
HPMX-5002 Pin Description
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
37
38
39
40
Mnemonic
IFOP1
DMOD
DMODOP
BUF1
BUF2
TCNT
TCSET
DATOP
RSSI
LKFIL
LKDET
REF
VCC3
VEE3
DIV1
DIV2
DIV3
PFD
VEE4
VCC4
AGC
VCOA
VCOB
VCOADJ
OSCOP
OSCOPB
VCC5
VEE5
IPDC
IP1
VCC1
VEE1
IF1
IFIP1
DC1A
VCC2
VEE2
I/O Type
Analog O/P
Analog I/P
Analog O/P
Analog I/P
Analog O/P
Analog DC
CMOS I/P
CMOS O/P
Analog O/P
Analog DC
CMOS O/P
Analog I/P
DC Supply
Ground
CMOS I/P
CMOS I/P
CMOS I/P
Analog O/P
Ground
DC Supply
Analog DC
Analog I/P
Analog O/P
Analog I/P
Analog O/P
Analog O/P
DC Supply
Ground
Analog DC
Analog I/P
DC Supply
Ground
Analog O/P
Analog I/P
Analog DC
DC Supply
Ground
Description
Output of IF amplifier, feeds quadrature network for discriminator
Input to discriminator mixer, driven by output of quadrature network
Output of discriminator mixer, drives external low-pass data filter
Noninverting input of buffer amplifier that drives the data slicer
Output of buffer amplifer that drives the data slicer
External capacitor connection which sets time constant for data slicer
Data slicer time constant select
Output bit stream from data slicer
Receive Signal Strength Indicator output
External capacitor connection which sets time constant for lock detector
Indicates that LO2 PLL is in lock status
Reference signal for LO2 PLL
PLL supply voltage
PLL ground
Controls divide ratio for reference frequency input to the LO2 PLL
Controls divide ratio for reference frequency input to the LO2 PLL
Controls divide ratio for VCO frequency input to the LO2 PLL
LO2 PLL phase/frequency detector charge pump output
LO2 VCO ground
LO2 VCO supply voltage
External capacitor connection to compensate LO2 VCO AGC loop
VCO tank force line
VCO tank sense line
Controls amplitude of buffered LO2 VCO output
Buffered LO2 output (+)
Buffered LO2 output (-)
1st IF supply voltage
1st IF ground
External capacitor connection for decoupling 1st IF bias point
1st IF input signal
IF limiting amplifier supply voltage
IF limiting amplifier ground
Downconverted signal from front-end mixer, drives external filter
(hi-Z output, open collector)
Input to IF limiting amplifier, driven by external filter
(600
Ω
impedance, internally set)
External capacitor connection for decoupling IF limiting amplifier
IF limiting amplifier supply voltage
IF limiting amplifier ground
7-109
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