M28C16A
M28C17A
16 Kbit (2Kb x8) Parallel EEPROM
FAST ACCESS TIME:
– 150ns at 5V
– 250ns at 3V
SINGLE SUPPLY VOLTAGE:
– 5V
±
10% for M28C16A and M28C17A
– 2.7V to 3.6V for M28C16-xxW
LOW POWER CONSUMPTION
FAST WRITE CYCLE
– 32 Bytes Page Write Operation
– Byte or Page Write Cycle: 5ms
ENHANCED END OF WRITE DETECTION
– Ready/Busy Open Drain Output
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
DESCRIPTION
The M28C16A and M28C17Aare 2K x8 low power
Parallel EEPROM fabricatedwith STMicroelectron-
ics proprietarysingle polysilicon CMOS technology.
The device offers fast access time with low power
dissipation and requires a 5V or 3V power supply.
Table 1. Signal Names
A0-A10
DQ0-DQ7
W
E
G
RB
V
CC
V
SS
Address Input
Data Input / Output
Write Enable
Chip Enable
Output Enable
Ready / Busy
Supply Voltage
Ground
28
1
PDIP28 (BS)
PLCC32 (KA)
28
1
SO28 (MS)
300 mils
TSOP28 (NS)
8 x13.4mm
Figure 1. Logic Diagram
VCC
11
A0-A10
8
DQ0-DQ7
W
E
M28C16A
M28C17A
RB
G
VSS
AI02109
August 1998
1/19
M28C16A, M28C17A
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7
22
M28C17A
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AI02110
VCC
W
DU
A8
A9
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
RB or NC
(1)
DU
VCC
W
DU
1 32
A8
A9
NC
NC
G
A10
E
DQ7
DQ6
M28C16A
M28C17A
25
17
AI02111
9
Warning:
NC = Not Connected, DU = Don’t Use.
Warning:
NC = Not Connected, DU = Don’t Use.
Note:
1. Pin 2 is either RB for M28C17A or NC
for M28C16A.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28C17A
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
DU
A8
A9
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
G
NC
A9
A8
DU
W
VCC
RB
NC
A7
A6
A5
A4
A3
22
DQ1
DQ2
VSS
NC
DQ3
DQ4
DQ5
21
28
1
M28C16A
15
14
7
8
AI02113
A7
NC
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
AI02112
Warning:
NC = Not Connected, DU = Don’t Use.
2/19
Warning:
NC = Not Connected, DU = Don’t Use.
M28C16A, M28C17A
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
V
CC
V
IO
V
I
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature Range
Supply Voltage
Input/Output Voltage
Input Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Value
– 40 to 85
– 65 to 150
– 0.3 to 6.5
– 0.3 to V
CC
+0.6
– 0.3 to 6.5
3000
Unit
°C
°
C
V
V
V
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Depends on range.
Table 3. Operating Modes
Mode
Read
Write
Standby / Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Note:
X = V
IH
or V
IL
E
V
IL
V
IL
V
IH
X
X
X
G
V
IL
V
IH
X
X
V
IL
V
IH
W
V
IH
V
IL
X
V
IH
X
X
DQ0 - DQ7
Data Out
Data In
Hi-Z
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
DESCRIPTION
(cont’d)
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshakingmode with Ready/Busy,
Data Polling and Toggle Bit. The M28C16A/17A
supports 32 byte page write operation.
PIN DESCRITPION
Addresses (A0-A10).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Output Enable (G).
The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
Data In/ Out (DQ0 - DQ7).
Data is written to or read
from the M28C16A/17A through the I/O pins.
Write Enable (W).
The Write Enable input controls
the writing of data to the M28C16A/17A.
Ready/Busy (RB).
Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle. Ready/Busy is available for the
M28C17A in PDIP, PLCC and SO packages, and
for the M28C16A in TSOP only.
OPERATION
In order to prevent data corruption and inadvertent
write operations during power-up, a Power On
Reset (POR) circuit resets all internal programming
cicuitry. Access to the memory in write mode is
allowed after a power-up as specified in Table 7.
Read
The M28C16A/17Ais accessed like a static RAM.
When E and G are low with W high, the data
addressed is presented on the I/O pins. The I/O
pins are high impedancewhen either G or E is high.
3/19
M28C16A, M28C17A
Figure 3. Block Diagram
E
G
W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A10
(Page Address)
ADDRESS
LATCH
64K ARRAY
A0-A5
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
AI01520
DQ0-DQ7
OPERATION
(cont’d)
Write
Write operations are initiated when both W and E
are low and G is high.The M28C16A/17Asupports
both E and W controlled write cycles. The Address
is latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Page Write
Page write allows up to 32 bytes to be consecu-
tively latched into the memory prior to initiating a
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
programming cycle. All bytes must be located in a
single page address, that is A5 - A10 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data up to a maxi-
mum of t
WHWH
after the rising edge of E or W which
ever occurs first. If a transition of E or W is not
detected within t
WHWH
, the internal programming
cycle will start.
Microcontroller Control Interface
The M28C16A/17A provides two write operation
status bits and one status pin that can be used to
minimize the system write cycle. These signals are
available on the I/O port bits DQ7 or DQ6 of the
memory during programming cycle only, or as the
RB signal on a separate pin.
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
4/19
M28C16A, M28C17A
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no longer driven.
≤
20ns
0.4V to 2.4V
0.8V to 2.0V
Figure 5. AC Testing Input Output Waveforms
4.5V to 5.5V Operating Voltage
2.4V
2.0V
0.8V
Figure 6. AC Testing Equivalent Load Circuit
VCC
0.4V
IOL
DEVICE
UNDER
TEST
IOH
OUT
2.7V to 3.6V Operating Voltage
VCC – 0.3V
0.5 VCC
0V
AI02101B
CL = 30pF
CL includes JIG capacitance
AI02114
Table 5. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note:
1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics for M28C16A and M28C17A
(T
A
= –40 to 85°C, V
CC
= 4.5V to 5.5V)
Symbol
I
LI
I
LO
I
CC (1)
I
CC1
I
CC2
(1)
(1)
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (TTL and CMOS inputs)
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
CC
E = V
IL
, G = V
IL
, f = 5MHz
E = V
IH
E > V
CC
– 0.3V
Min
Max
10
10
25
1
50
Unit
µA
µA
mA
mA
µ
A
V
V
V
V
V
IL
V
IH
V
OL
V
OH
–0.3
2
I
OL
= 2.1 mA
I
OH
= –400
µA
2.4
0.8
V
CC
+ 0.5
0.4
Note:
1. All I/O’s open circuit.
5/19
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