M27C322
32 Mbit (2Mb x16) UV EPROM and OTP EPROM
s
5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
ACCESS TIME: 80ns
WORD-WIDE CONFIGURABLE
32 Mbit MASK ROM REPLACEMENT
LOW POWER CONSUMPTION
– Active Current 50mA at 5MHz
1
42
42
s
s
s
s
– Stand-by Current 100µA
s
s
s
1
PROGRAMMING VOLTAGE: 12V ± 0.25V
PROGRAMMING TIME: 50µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 0034h
FDIP42W (F)
PDIP42 (P)
Figure 1. Logic Diagram
DESCRIPTION
The M27C322 is a 32 Mbit EPROM offered in the
UV range (ultra violet erase). It is ideally suited for
microprocessor systems requiring large data or
program storage. It is organised as 2 MWords of
16 bit. The pin-out is compatible with a 32 Mbit
Mask ROM.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C322 is offered in PDIP42 package.
VCC
21
A0-A20
16
Q0-Q15
E
GVPP
M27C322
VSS
AI02156
April 2000
1/13
M27C322
Figure 2A. DIP Connections
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
GVPP
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
42
2
41
3
40
4
39
5
38
6
37
7
36
35
8
9
34
10
33
M27C322
32
11
31
12
30
13
29
14
28
15
27
16
26
17
18
25
24
19
20
23
22
21
AI02157
Table 1. Signal Names
A0-A20
Address Inputs
Data Outputs
Chip Enable
Output Enable / Program Supply
Supply Voltage
Ground
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
A20
VSS
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q0-Q15
E
GV
PP
V
CC
V
SS
DEVICE OPERATION
The operating modes of the M27C322 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C322 has a word-wide organization. Chip
Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of GV
PP
, assuming that E has been low and the
addresses have been stable for at least t
AVQV
-
t
GLQV
.
Standby Mode
The M27C322 has a standby mode which reduces
the supply current from 50mA to 100µA. The
M27C322 is placed in the standby mode by apply-
ing a CMOS high signal to the E input.When in the
standby mode, the outputs are in a high imped-
ance state, independent of the GV
PP
input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while GV
PP
should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
2/13
M27C322
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Program Inhibit
Standby
Electronic Signature
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
E
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IL
GV
PP
V
IL
V
IH
V
PP
V
PP
X
V
IL
A9
X
X
X
X
X
V
ID
Q15-Q0
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
0
Q6
0
0
Q5
1
1
Q4
0
1
Q3
0
0
Q2
0
1
Q1
0
0
Q0
0
0
Hex Data
20h
34h
Note: Outputs Q15-Q8 are set to '0'.
3/13
M27C322
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
12
Unit
pF
pF
Note: 1. Sampled only, not 100% tested.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor is used on every device between V
CC
and V
SS
. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween V
CC
and V
SS
for every eight devices. This
capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.
4/13
M27C322
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; V
CC
= 5V ± 10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0v
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, GV
PP
= V
IL
, I
OUT
= 0mA,
f = 8MHz
I
CC
Supply Current
E = V
IL
, GV
PP
= V
IL
, I
OUT
= 0mA,
f = 5MHz
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
I
OL
= 2.1mA
I
OH
= –400µA
2.4
E = V
IH
E > V
CC
– 0.2V
V
PP
= V
CC
–0.3
2
50
1
100
10
0.8
V
CC
+ 1
0.4
mA
mA
µA
µA
V
V
V
V
Min
Max
±1
±10
70
Unit
µA
µA
mA
I
CC
1
I
CC
2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; V
CC
= 5V ± 10%; V
PP
= V
CC
)
M27C322
Symbol
Alt
Parameter
Test Condition
-80
(3)
Min
t
AVQV
t
ELQV
t
GLQV
t
EHQZ (2)
t
GHQZ (2)
t
AXQX
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output
Transition
E = V
IL
, GV
PP
= V
IL
GV
PP
= V
IL
E = V
IL
GV
PP
= V
IL
E = V
IL
E = V
IL
, GV
PP
= V
IL
0
0
5
Max
80
80
40
40
40
0
0
5
-100
Min
Max
100
100
50
40
40
ns
ns
ns
ns
ns
ns
Unit
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
5/13
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