CAT24C164
16 kb CMOS Serial
EEPROM, Cascadable
Description
The CAT24C164 is a 16 kb CMOS cascadable Serial EEPROM
device organized internally as 128 pages of 16 bytes each, for a total of
2048 x 8 bits. The device supports both the Standard (100 kHz) as well
as Fast (400 kHz) I
2
C protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAT24C164 devices on the same bus.
Features
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SOIC−8
W SUFFIX
CASE 751BD
TDFN−8
VP2 SUFFIX
CASE 511AK
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•
•
•
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•
Supports Standard and Fast I
2
C Protocol
1.8 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
PDIP, SOIC, TSSOP and TDFN 8−lead Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
A
0
A
1
A
2
V
SS
1
V
CC
WP
SCL
SDA
PDIP (L), SOIC (W),
TSSOP (Y), TDFN (VP2)
(Top View)
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTION
SCL
CAT24C164
SDA
Pin Name
A
0
, A
1
, A
2
SDA
SCL
WP
V
SS
V
CC
V
SS
Function
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
A
2
, A
1
, A
0
WP
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 2
1
Publication Order Number:
CAT24C164/D
CAT24C164
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
–0.5 to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(
V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Parameter
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
−0.5
V
CC
x 0.7
Min
Max
1
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
mA
mA
mA
mA
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Symbol
C
IN
(Note 4)
C
IN
(Note 4)
I
WP
(Note 5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 1.8 V
V
IN
> V
IH
Conditions
Max
8
6
200
150
100
1
Units
pF
pF
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
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CAT24C164
Table 5. A.C. CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C.) (Note 6)
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
(Note 7)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 7)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 7, 8)
6.
7.
8.
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3 mA (V
CC
≥
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
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CAT24C164
Power-On Reset (POR)
CAT24C164 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A CAT24C164 device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.
Pin Description
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A
0
, A
1
and A
2
:
The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
The CAT24C164 can be made compatible with the
CAT24C16 by tying A
2
, A
1
and A
0
to V
SS
or by leaving A
2
,
A
1
and A
0
float.
WP:
The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAT24C164 supports the Inter−Integrated Circuit
2
C) Bus data transmission protocol, which defines a device
(I
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C164 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I
2
C Bus Protocol
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of the
particular Slave device it is requesting. The most significant
bit of the 8−bit slave address is fixed as 1. (see Figure 3). The
next three significant bits (A
2
, A
1
, A
0
) are the device address
bits and define which device or which part of the device the
Master is accessing (The A
1
bit must be the compliment of
the A
1
input pin signal). Up to eight CAT24C164 devices
may be individually addressed by the system. The next three
bits are used as the three most significant bits of the data
word address. The last bit of the slave address specifies
whether a Read or Write operation is to be performed. When
this bit is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9
th
clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
th
clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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CAT24C164
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. START/STOP Conditions
1
A2
A1
A0
a
10
a
9
a
8
R/W
CAT24C164
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t
AA
)
ACK SETUP (≥ t
SU:DAT
)
Figure 4. Acknowledge Timing
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
HD:STA
t
HIGH
t
LOW
t
R
t
HD:DAT
t
SU:DAT
t
SU:STO
t
DH
t
BUF
Figure 5. Bus Timing
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