HS-80C85RH
February 1996
Radiation Hardened
8-Bit CMOS Microprocessor
Description
The HS-80C85RH is an 8-bit CMOS microprocessor fabri-
cated using the Intersil radiation hardened self-aligned junc-
tion isolated (SAJI) silicon gate technology. Latch-up free
operation is achieved by the use of epitaxial starting material
to eliminate the parasitic SCR effect seen in conventional
bulk CMOS devices.
The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software com-
patible with the HMOS device. The HS80C85RH is designed
for operation with a single 5 volt power supply. Its high level
of integration allows the construction of a radiation hardened
microcomputer system with as few as three ICs (HS-
80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/
56RH RAM I/O.
Features
• Devices QML Qualified in Accordance With
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95824 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 10
5
RAD(Si)
- Transient Upset > 1 x 10
8
RAD(Si)/s
- Latch-up Free > 1 x 10
12
RAD(Si)/s
• Low Standby Current 500µA Max
• Low Operating Current 5.0mA/MHz (X
1
Input)
• Electrically Equivalent to Sandia SA 3000
• 100% Software Compatible with INTEL 8085
• Operation from DC to 2MHz, Post Radiation
• Single 5 Volt Power Supply
• On-Chip Clock Generator and System Controller
• Four Vectored Interrupt Inputs
• Completely Static Design
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55
o
C to +125
o
C
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835, CDIP2-T40
TOP VIEW
X1 1
X2 2
RESET OUT 3
SOD 4
SID 5
TRAP 6
RST 7.5 7
RST 6.5 8
RST 5.5 9
INTR 10
INTA 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
40 VDD
39 HOLD
38 HLDA
37 CLOCK OUT
36 RESET IN
35 READY
34 IO / M
33 S1
32 RD
31 WR
30 ALE
29 S0
28 A15
27 A14
26 A13
25 A12
24 A11
23 A10
22 A9
21 A8
X1
X2
RESET
OUT
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
AD0
AD1
AD2
AD3
AD4
NC
NC
AD5
AD6
AD7
42 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
INTERSIL OUTLINE K42.A
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
HOLD
HLDA
CLOCK
OUT
RESET
IN
READY
IO / M
S1
RD
WR
ALE
S0
A15
A14
A13
A12
A11
A10
A9
A8
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518054
3036.2
HS-80C85RH
Ordering Information
PART NUMBER
5962R9582401QQC
5962R9582401QXC
5962R9582401VQC
5962R9582401VXC
HS1-80C85RH/SAMPLE
HS9-80C85RH/SAMPLE
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
Sample
Sample
PACKAGE
40 Lead SBDIP
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
Functional Diagram
INTA
INTR
RST
5.5
RST
6.5
RST
7.5 TRAP
SID
SOD
INTERRUPT CONTROL
SERIAL I/O CONTROL
8-BIT
INTERNAL DATA BUS
ACCUMU-
LATOR (8)
TEMP REG
(8)
FLAG (5)
FLIP FLOPS
INSTRUCTION
REGISTER (8)
B REG (8)
D REG (8)
H REG (8)
C REG (8)
REGISTER ARRAY
DATA ADDRESS
BUFFER (8)
AD1-AD0
ADDRESS
BUS
E REG (8)
L REG (8)
ARITHMETIC
LOGIC
UNIT
(ALU) (8)
POWER
SUPPLY
X1
X2
VDD
GND
CLK
GEN
INSTRUCTION
DECODER
AND MACHINE
CYCLE
ENCODING
STACK POINTER (16)
PROGRAM COUNTER (16)
INCREMENTER
DECREMENTER
ADDRESS LATCH (16)
TIMING AND CONTROL
CONTROL
STATUS
DMA
RESET
ADDRESS
BUFFER (8)
READY
CLK
OUT
RD
WR
ALE
S0
S1
IO/M
HOLD
HLDA
RESET
IN
RESET
OUT
A15-A8
ADDRESS
BUS
Spec Number
2
518054
HS-80C85RH
Pin Description
SYMBOL
A8 - A15
PIN
NUMBER
21-28
TYPE
O
DESCRIPTION
Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,
3-stated during Hold and Halt modes and during RESET.
Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on
the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus
during the second and third clock cycles.
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the
address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guar-
antee setup and hold times for the address information. The falling edge of ALE can also be used
to strobe the status information. ALE is never 3-stated.
Machine Cycle Status:
IO/M
0
0
1
1
0
1
1
T
T
T
S1
0
1
0
1
1
1
1
0
X
X
S0
1
0
1
0
1
1
1
0
X
X
Status
Memory write
Memory write
I/O write
I/O read
Opcode fetch
Opcode fetch
Interrupt acknowledge
Halt
Hold
Reset
AD0-7
12-19
I/O
ALE
32
O
S0, S1, and
IO/M
31, 35,
& 36
O
T = 3-State (high impedance)
X = Unspecified
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used
to latch the state of these lines.
RD
34
O
Read Control: A low level on RD indicates the selected memory or I/O device is to be read and
that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and dur-
ing RESET.
Write Control: A low level on WR indicates the data on the Data Bus is to be written into the se-
lected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and
Halt modes and during RESET.
Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral
is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock
cycles for READY to go high before completing the read or write cycle. READY must conform to
specified setup and hold times.
Hold: Indicates that another master is requesting the use of the address and data buses. The
cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion
of the current bus transfer. Internal processing can continue. The processor can regain the bus
only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data Bus, RD,
WR, and IO/M lines are 3-stated.
Hold Acknowledge: Indicates that the cpu has received the HOLD request and that it will relin-
quish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu
takes the bus one half clock cycle after HLDA goes low.
WR
33
O
READY
35
I
HOLD
39
I
HLDA
38
O
Spec Number
3
518054
HS-80C85RH
Pin Description
SYMBOL
INTR
(Continued)
PIN
NUMBER
10
TYPE
I
DESCRIPTION
Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to
the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a
RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR
is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is
accepted.
Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruc-
tion cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some
other interrupt port.
Restart Interrupts: These three inputs have the same timing as INTR except they cause an
internal RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher
priority than INTR. In addition, they may be individually masked out using the SIM instruction.
Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as
INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority
of any interrupt. (See Table 6.)
Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.
The data and address buses and the control lines are 3-stated during RESET and because of
the asynchronous nature of RESET the processor’s internal registers and flags may be altered
by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connec-
tion to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN
must remain low for at least 10 “clock cycle” after minimum VDD has been reached. For proper
reset operation after the power-up duration, RESET IN should be kept low a minimum of three
clock periods. The CPU is held in the reset condition as long as RESET IN is applied.
Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal
is synchronized to the processor clock and lasts an integral number of clock periods.
X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator.
X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to
give the processor’s internal operating frequency.
Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input
period.
Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM
instruction is executed.
Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.
Power: +5V supply.
Ground: Reference.
INTA
11
O
RST 5.5
RST 6.5
RST 7.5
9
8
7
I
TRAP
6
I
RESET IN
36
I
RESET OUT
3
O
X1
X2
1
2
I
O
CLK
37
O
SID
5
I
SOD
VCC
GND
4
40
20
O
I
I
RESET IN
R1
VDD
TYPICAL POWER-ON RESET RC VALUES
†
R1 = 75KΩ
C1 = 1µF
C1
†
Values may have to vary due to applied power supply ramp up time.
FIGURE 1. POWER-ON RESET CIRCUIT
Spec Number
4
518054
Specifications HS-80C85RH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
Typical Derating Factor. . . . . . . . . . .2.0mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance
θ
JA
θ
JC
o
C/W
SBDIP Package. . . . . . . . . . . . . . . . . . . .
45
10
o
C/W
o
C/W
Ceramic Flatpack Package . . . . . . . . . . .
77
13
o
C/W
Maximum Package Power Dissipation at +125
o
C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.65W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2mW/
o
C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 13.0mW/
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
7, 8A, 8B
LIMITS
TEMPERATURE
-55
o
C, +25
o
C, or
+125
o
C
-55
o
C, +25
o
C, or
+125
o
C
-55
o
C, +25
o
C, or
+125
o
C
-55
o
C, +25
o
C, or
+125
o
C
-55
o
C, +25
o
C, or
+125
o
C
-55
o
C, +25
o
C, or
+125
o
C
MIN
-1.0
VDD -0.5
-
-
-
-
MAX
1.0
-
0.5
500
5.0
-
UNITS
µA
V
V
µA
mA/MHz
-
PARAMETER
Input Leakage
Current
High Level Output
Voltage
Low Level Output
Voltage
Static Current
Operating Supply
Current (Note 2)
Functional Tests
SYMBOL
IIH or
IIL
VOH
VOL
IDDSB
IDDOP
FT
CONDITIONS
VDD = 5.25V, VI = VDD
or GND
VDD = 4.75V, IOH = -1.0mA
VDD = 5.25V, IOL = 1.0mA,
VDD = 5.25V, Clock Out = Hi
and Low
VDD = 5.25V, f = 1MHz
(Note 2)
VDD = 4.75V and 5.25V,
TCYC = 500ns,
VOL
≤
VDD/2, VOH
≥
VDD/2
NOTES:
1. All devices guaranteed at worst case limits and over radiation.
2. Operating supply current (IDDOP) is proportional to crystal frequency. Parts are tested at 1MHz
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
LIMITS
TEMPERATURE
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
MIN
40
100
-
-
30
50
300
300
875
-
MAX
-
-
115
115
250
275
-
-
-
70
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
CLK Low Time (Standard CLK Loading)
CLK High Time (Standard CLK Loading)
CLK Rise Time
CLK Fall Time
X1 Rising to CLK Rising
X1 Rising to CLK Falling
A8-15 Valid to Leading Edge of Control (Note 5)
A0-7 Valid to Leading Edge of Control
A0-15 Valid to Valid Data In
Address Float After Leading Edge of READ
(INTA)
SYMBOL
T1
T2
Tr
Tf
TXKR
TXKF
TAC
TACL
TAD
TAFR
Spec Number
5
518054
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