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CY39030Z144-125BBI

Description
Loadable PLD, 10ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,57 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

CY39030Z144-125BBI Overview

Loadable PLD, 10ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144

CY39030Z144-125BBI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeBGA
package instructionBGA,
Contacts144
Reach Compliance Codeunknown
JESD-30 codeS-PBGA-B144
Dedicated input times
Number of I/O lines92
Number of terminals144
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize0 DEDICATED INPUTS, 92 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programmable logic typeLOADABLE PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum supply voltage1.95 V
Minimum supply voltage1.65 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
PRELIMINARY
Delta39K™ ISR™
CPLD Family
CPLDs at FPGA Densities™
Features
•High density
— 15K to 350K usable gates
— 256 to 5376 macrocells
— 92 to 520 maximum I/O pins
— 12 Dedicated Inputs including 4 clock pins, 4 global
control signal pins and 4 JTAG interface pins for
reconfigurability
•Embedded Memory
— 40K to 840K bits embedded SRAM
• 32K to 672K bits of (single port) Cluster memory
• 8K to 168K bits of (dual port) Channel memory
•High speed - 250-MHz in-system operation
•AnyVolt™ interface
— 3.3V, 2.5V and 1.8V V
CC
versions available
— 3.3V, 2.5V and 1.8V I/O capability on all versions
• Low Power Operation
0.18-µm 6-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
Standby current as low as 100
µA
at 1.8V V
CC
•Simple timing model
— No penalty for using full 16 product terms / macrocell
— No delay for single product term steering or sharing
•Flexible clocking
— 4 synchronous clocks per device
— 1 spread-aware PLL drives all 4 clock networks
— Locally generated Product Term clock
— Clock polarity control at each register
•Carry-chain logic for fast and efficient arithmetic opera-
tions
•Multiple I/O standards supported
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
•Compatible with NOBL™, ZBT™, and QDR™ SRAMs
•Programmable slew rate control on each I/O pin
•User-Programmable Bus Hold capability on each I/O pin
•Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)
•Compact PCI hot swap compatible
•Multiple package/pinout offering across all densities
— 144 to 676 pins in PQFP, BGA and FBGA packages
— Same pinout for 3.3V/2.5V and 1.8V devices
— Simplifies design migration across density
— Self-Boot™ solution in BGA and FBGA packages
•In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
•IEEE1149.1 JTAG boundary scan
Development Software
•Warp™
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing.
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 95, 98 & NT for $99
— Supports all Cypress Programmable Logic Products
Delta39K™ ISR CPLD Family Members
Typical
Gates
[1]
8K–24K
16K–48K
23K–72K
46K–144K
77K–241K
92K–288K
115K–361K
161K–505K
Cluster
memory
(Kbits)
32
64
96
192
320
384
480
672
Channel
memory
(Kbits)
8
16
24
48
80
96
120
168
Maximum
I/O Pins
134
176
218
302
386
428
470
520
f
MAX2
(MHz)
256
238
238
222
181
181
167
154
Speed - t
PD
Pin-to-Pin
(ns)
6.5
7.0
7.0
7.5
8.5
8.5
8.5
9.0
Standby I
CC
[2]
T
A
=25°C
3.3/2.5V
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
1.8V
100
µA
200
µA
300
µA
600
µA
1250
µA
1250
µA
1500
µA
2100
µA
Device
39K15
39K30
39K50
39K100
39K165
39K200
39K250
39K350
Macrocells
256
512
768
1536
2560
3072
3840
5376
Note:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby I
CC
values are with PLL not utilized, no output load and stable inputs
Cypress Semiconductor Corporation
Document #: 38-03039 Rev. **
3901 North First Street
San Jose
CA 95134
• 408-943-2600
Revised April 4, 2001
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