16 MBit Synchronous DRAM
HYB 39S16400/800/160CT-8/-10
• High Performance:
-8
-10
100
10
7
12
8
Units
MHz
ns
ns
ns
ns
f
CK(MAX.)
t
CK3
t
AC3
t
CK2
t
AC2
•
•
•
•
•
125
8
6
10
6
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control
• Dual Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64 ms
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V
±
0.3 V Power Supply
• LVTTL Interface
• Plastic Packages:
P-TSOPI-44 400mil width (× 4,
×
8)
P-TSOPII-50 400mil width (× 16 )
• -8 version for PC100 applications
Fully Synchronous to Positive Clock Edge
0 to 70
°C
operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence:
Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8
• Full page (optional) for sequencial wrap
around
The HYB39S16400/800/160CT are dual bank Synchronous DRAM’s based on SIEMENS 0.25
µm
process and organized as 2 banks
×
2 MBit
×
4, 2 banks
×
1 MBit
×
8 and 2 banks
×
512 kbit
×
16 respectively. These synchronous devices achieve high speed data transfer rates up to 125
MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output
data to a system clock. The chip is fabricated with SIEMENS’ advanced 16 MBit DRAM process
technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to
occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up
to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V
±
0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
1998-10-01
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Ordering Information
Type
LVTTL-Version
HYB 39S16400CT-8
HYB 39S16400CT-10
HYB 39S16800CT-8
HYB 39S16800CT-10
HYB 39S16160CT-8
HYB 39S16160CT-10
on request
on request
on request
on request
on request
on request
P-TSOPII-44-1 400 mil
P-TSOPII-44-1 400 mil
P-TSOPII-44-1 400 mil
P-TSOPII-44-1 400 mil
P-TSOPII-50 400 mil
P-TSOPII-50 400 mil
125 MHz 2B
×
2 M
×
4 SDRAM, PC100 2-2-2
100 MHz 2B
×
2 M
×
4 SDRAM, PC66 2-2-2
125 MHz 2B
×
1 M
×
8 SDRAM, PC100 2-2-2
100 MHz 2B
×
1 M
×
8 SDRAM, PC66 2-2-2
125 MHz 2B
×
512k
×
16 SDRAM
100 MHz 2B
×
512k
×
1 SDRAM
Ordering Code
Package
Description
Pin Names
CLK
CKE
CS
RAS
CAS
WE
A0 - A10
A11 (BS)
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQ
DQM, LDQM,
UDQM
Data Input /Output
Data Mask
Power (+ 3.3 V)
Ground
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not connected
V
DD
V
SS
V
DDQ
V
SSQ
NC
Semiconductor Group
2
1998-10-01
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
V
DD
N.C.
V
SSQ
DQ0
V
DDQ
N.C.
V
SSQ
DQ1
V
DDQ
N.C.
N.C.
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SPP03401
V
SS
N.C.
V
SSQ
DQ3
V
DDQ
N.C.
V
SSQ
DQ2
V
DDQ
N.C.
N.C.
DQM
CLK
CKE
N.C.
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
SSQ
DQ1
V
DDQ
DQ2
V
SSQ
DQ3
V
DDQ
N.C.
N.C.
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SPP03402
V
SS
DQ7
V
SSQ
DQ6
V
DDQ
DQ5
V
SSQ
DQ4
V
DDQ
N.C.
N.C.
DQM
CLK
CKE
N.C.
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SPP03403
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C.
UDQM
CLK
CKE
N.C.
A9
A8
A7
A6
A5
A4
V
SS
Pin Configuration
Semiconductor Group
3
1998-10-01
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description
Pin
CLK
CKE
Type
Input
Input
Signal Polarity Function
Pulse
Level
Positive The system clock input. All of the SDRAM inputs are sampled on
Edge
the rising edge of the clock.
Active
High
Active
Low
Activates the CLK signal when high and deactivates the CLK
signal when low, thereby inititiates either the Power Down mode,
Suspend mode or the Self Refresh mode.
CS enables the command decoder when low and disables the
command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations
continue.
When sampled at the positive rising edge of the clock, CAS,
RAS, and WE define the command to be executed by the
SDRAM.
During a Bank Activate command cycle, A0 - A10 defines the
row address (RA0 - RA10) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0 - A9 defines the
column address (CA0 - CAn) when sampled at the rising clock
edge. CAn depends from the SDRAM organisation.
4M
×
4 SDRAM CAn = CA9
2M
×
8 SDRAM CAn = CA8
1M
×
16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke auto-
precharge operation at the end of the burst read or write cycle. If
A10 is high, autoprecharge is selected and A11 defines the bank
to be precharged (low = bank A, high = bank B). If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction
with A11 to control which bank(s) to precharge. If A10 is high,
both bank A and bank B will be precharged regardless of the
state of A11. If A10 is low, then A11 is used to define which bank
to precharge.
Selects which bank is to be active. A11 low selects bank A and
A11 high selects bank B.
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
The Data Input/Output mask places the DQ buffers in a high
impedance state when sampled high. In Read mode, DQM has
a latency of two clock cycles and controls the output buffers like
an output enable. In Write mode, DQM has a latency of zero and
operates as a word mask by allowing input data to be written if it
is low but blocks the write operation if DQM is high.
CS
Input
Pulse
RAS
CAS
WE
A0 -
A10
Input
Pulse
Active
Low
–
Input
Level
A11
(BS)
DQx
Input
Level
–
–
Active
High
Input Level
Output
Pulse
DQM, Input
LDQM,
UDQM
Semiconductor Group
4
1998-10-01
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description
(cont’d)
Pin
Type
Signal Polarity Function
–
–
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
V
DD
V
SS
V
DDQ
V
SSQ
Supply –
Supply –
CKE
CKE Buffer
Self
Refresh Clock
Row Decoder
2048
Row
Address
Counter
Bank A
Row/Column
Select
11
1024
4
Sense Amplifiers
Column Decoder
and DQ Gate
8
2048 x 1024
Memory Bank A
CLK
CLK Buffer
Predecode A
8
12
11
Mode Register
8
3
Sequential
Control
Bank B
Data Input/Output Buffers
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
CS
Address Buffers (12)
12
3
Sequential
Control
Bank A
Data Latches
DQ0
DQ1
DQ2
DQ3
CS Buffer
Data Latches
8
Command Decoder
RAS
RAS Buffer
11
Predecode B
Column Decoder
and DQ Gate
Bank B
Row/Column
Sense Amplifiers
1024
Memory Bank B
2048 x 1024
2048
SPB02835
CAS
CAS Buffer
Select
WE
WE Buffer
DQM
DQM Buffer
Row Decoder
Block Diagram for HYB 39S16400CT (2 banks
×
2 M
×
4 SDRAM)
Semiconductor Group
5
1998-10-01
MicroPython Open Source section
京公网安备 11010802033920号
EEWORLD
