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ICS8432DYI-101LFT

Description
8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
Categorysemiconductor    logic   
File Size158KB,18 Pages
ManufacturerICS ( IDT )
Websitehttp://www.icst.com
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ICS8432DYI-101LFT Overview

8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32

ICS8432DYI-101LFT Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals32
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.46 V
Minimum supply/operating voltage3.14 V
Rated supply voltage3.3 V
Processing package description7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
packaging shapeSQUARE
Package SizeFLATPACK, low PROFILE
surface mountYes
Terminal formGULL WING
Terminal spacing0.8000 mm
terminal coatingMATTE Tin
Terminal locationFour
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
series8432
Enter conditionsDifferential MUX
Logic IC typePhase locked loop clock driver
Number of inverted outputs0.0
Real output number2
Maximum same-side bending0.0150 ns
Max-Min frequency700 MHz
Integrated
Circuit
Systems, Inc.
ICS8432I-101
700MH
Z
,
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK, nCLK or TEST_CLK maximum input frequency: 40MHz
Output frequency range: 25MHz to 700MHz
VCO range: 250MHz to 700MHz
Accepts any single-ended input signal on CLK input
with resistor bias on nCLK input
Parallel interface for programming counter
and output dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS8432I-101 is a general purpose, dual out-
put Differential-to-3.3V LVPECL high frequency
HiPerClockS™
synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8432I-101 has a selectable
TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts
LVCMOS or LVTTL input levels and translates them to 3.3V
LVPECL levels. The CLK, nCLK pair can accept most standard
differential input levels. The VCO operates at a frequency range
of 250MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of the input differential or single ended
reference frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the
configuration logic. The low phase noise characteristics of the
ICS8432I-101 makes it an ideal clock source for Gigabit
Ethernet and SONET applications.
ICS
B
LOCK
D
IAGRAM
VCO_SEL
CLK_SEL
TEST_CLK
CLK
nCLK
0
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
nCLK
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
1
M5
M6
M7
M8
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
24
23
22
CLK
TEST_CLK
CLK_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
÷
M
VCO
0
1
÷
1
÷
2
÷
4
÷
8
FOUT0
nFOUT0
FOUT1
nFOUT1
N0
N1
nc
V
EE
ICS8432I-101
21
20
19
18
17
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8432DYI-101
www.icst.com/products/hiperclocks.html
1
REV. A MAY 23, 2005

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Description 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
Number of functions 1 1 1 1 1 1 1
Number of terminals 32 32 32 32 32 32 32
Maximum operating temperature 85 Cel 85 Cel 85 Cel 85 Cel 85 Cel 85 Cel 85 Cel
Minimum operating temperature -40 Cel -40 Cel -40 Cel -40 Cel -40 Cel -40 Cel -40 Cel
Maximum supply/operating voltage 3.46 V 3.46 V 3.46 V 3.46 V 3.46 V 3.46 V 3.46 V
Minimum supply/operating voltage 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V
Rated supply voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Processing package description 7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 7 × 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
Lead-free Yes Yes Yes Yes Yes Yes Yes
EU RoHS regulations Yes Yes Yes Yes Yes Yes Yes
state ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
packaging shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package Size FLATPACK, low PROFILE FLATPACK, low PROFILE FLATPACK, low PROFILE FLATPACK, low PROFILE FLATPACK, low PROFILE FLATPACK, low PROFILE FLATPACK, low PROFILE
surface mount Yes Yes Yes Yes Yes Yes Yes
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal spacing 0.8000 mm 0.8000 mm 0.8000 mm 0.8000 mm 0.8000 mm 0.8000 mm 0.8000 mm
terminal coating MATTE Tin MATTE Tin MATTE Tin MATTE Tin MATTE Tin MATTE Tin MATTE Tin
Terminal location Four Four Four Four Four Four Four
Packaging Materials Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
series 8432 8432 8432 8432 8432 8432 8432
Enter conditions Differential MUX Differential MUX Differential MUX Differential MUX Differential MUX Differential MUX Differential MUX
Logic IC type Phase locked loop clock driver Phase locked loop clock driver Phase locked loop clock driver Phase locked loop clock driver Phase locked loop clock driver Phase locked loop clock driver Phase locked loop clock driver
Number of inverted outputs 0.0 0.0 0.0 0.0 0.0 0.0 0.0
Real output number 2 2 2 2 2 2 2
Maximum same-side bending 0.0150 ns 0.0150 ns 0.0150 ns 0.0150 ns 0.0150 ns 0.0150 ns 0.0150 ns
Max-Min frequency 700 MHz 700 MHz 700 MHz 700 MHz 700 MHz 700 MHz 700 MHz
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