1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol Parameter
(1)
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.2
3.7
Max.
5.0
8.0
Unit
pF
pF
3267 lnk 02
NOTE:
1. This parameter is measured at characterization but not tested.
*NC = No connect
9.9
2
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Name
REF_IN
FEEDBACK
Q4
1-4
Q8
1-8
Q5
1-5
I/O
I
I
O
O
O
I
I
O
I
I
O
Reference clock input.
Feedback input to phase detector.
BANK1 clock outputs.
BANK2 clock outputs.
BANK3 clock outputs.
Output enable controls for BANKS 1, 2 and 3 (Active LOW).
Control lines to select output configuration (see table).
Dedicated PLL feedback output.
Asynchronous reset (Active LOW).
Disables phase-lock for low frequency testing (Refer to functional block diagram).
PLL "LOCK" indicator (HIGH when PLL is locked).
3267 tbl 03
Description
OE
1-3
CNTRL1-4
Q_FB
RST
PLL_EN
LOCK
OUTPUT FREQUENCY CONFIGURATION AND INPUT FREQUENCY RANGE TABLE
MODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CNTRL
4 3 2 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Q_FEEDBACK
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-3)
F (divide-by-3)
F (divide-by-3)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-4)
F (divide-by-4)
F (divide-by-4)
Q_BANK1
(4 outputs)
Q_BANK2
(8 outputs)
F
F
F
F/2
F/3
3F
F
3F
2F
F
F
F
F/2
2F
2F
2F
Q_BANK3
(5 outputs)
F
F/2
F
F/2
F
F
3F
3F
2F
2F
F
F/2
F
4F
2F
F
F
IN
Range
50-100MHz
50-100MHz
50-100MHz
50-100MHz
50-100MHz
16.7-33.3MHz
16.7-33.3MHz
16.7-33.3MHz
25-50MHz
25-50MHz
25-50MHz
25-50MHz
25-50MHz
12.5-25MHz
12.5-25MHz
12.5-25MHz
3267 tbl 04
F
F
F
F
F
3F
3F
3F
2F
2F
2F
2F
2F
4F
4F
4F
9.9
3
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to 70°C, V
CC
= 3.3V
±
0.3V
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Input LOW Level
(Input and I/O pins)
Input HIGH Current (Input pins)
Input LOW Current (Input pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Quiescent Power Supply Current
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= GND
V
O
= V
CC
V
O
= GND
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= Max., V
IN
= GND or V
CC
—
—
—
—
—
–36
50
—
—
—
—
—
–0.7
–75
75
—
6
±1
±1
±1
±1
–1.2
V
mA
mA
mA
µA
µA
Guaranteed Logic LOW Level
Test Conditions
(1)
Guaranteed Logic HIGH Level
Min.
2.0
2.0
–0.5
Typ.
(2)
—
—
—
Max.
5.5
V
CC
+0.5
0.8
V
Unit
V
3267 tbl 05
TYPE 1 DRIVER - FCT3932
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –0.1mA
V
IN
= V
IH
or V
IL
V
CC
= 3.0V
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –8mA
I
OL
= 0.1mA
I
OL
= 16mA
I
OL
= 24mA
2.2
(4)
—
—
—
2.4
—
0.2
0.3
—
0.2
0.4
0.5
3267 tbl 06
Min.
Typ.
(2)
V
CC
–0.2
—
Max.
—
Unit
V
V
OL
Output LOW Voltage
V
TYPE 2 DRIVER - FCT32932
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –0.1mA
V
IN
= V
IH
or V
IL
V
CC
= 3.0V
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –8mA
I
OL
= 0.05mA
I
OL
= 4mA
I
OL
= 8mA
2.4
(4)
—
—
—
3.0
—
0.2
0.3
—
0.2
0.4
0.5
3267 tbl 07
Min.
Typ.
(2)
V
CC
–0.2
—
Max.
—
Unit
V
V
OL
Output LOW Voltage
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. V
OH
= V
CC
–0.6V at rated current.
9.9
4
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol
t
RISE/FALL
Frequency
Parameter
Rise/Fall Times REF_IN input (0.8V to 2.0V)
Input Frequency REF_IN input
Modes 0, 1, 2, 3, 4
Modes 5, 6, 7
Modes 8, 9, 10, 11, 12
Modes 13, 14, 15
Duty Cycle
Input Duty Cycle, REF_IN input
Min.
—
50
16.7
25
12.5
25
Max.
3.0
100
33.3
50
25
75
%
3267 tbl 09
Unit
ns
MHz
OUTPUT FREQUENCY SPECIFICATIONS
Mode
0, 1, 2, 3,4
Operating
frequency
5, 6, 7
8, 9, 10, 11, 12
Operating
frequency
Operating
frequency
13, 14, 15
Operating
frequency
Parameter
F,
F
Outputs
F/2 Outputs
F/3 Outputs
3F Outputs
F Outputs
2F Outputs
F Outputs
F/2 Outputs
4F Outputs
2F Outputs
F Outputs
Min.
50
25
16.7
50
16.7
50
25
12.5
50
25
12.5
Max.
100
50
33.3
100
33.3
100
50
25
100
50
25
3267 tbl 10
Unit
MHz
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Total Power Supply Current
(5,6)
V
CC
= Max.
Test Conditions
(1)
V
IN
= V
CC
–0.6V
(3)
F = 50Mhz
Min.
—
—
Typ.
(2)
2.0
72
Max.
30
Unit
µA
µA/
MHz/
bit
mA
I
C
V
CC
= Max.
V
IN
= V
CC
All Outputs Open
V
IN
= GND
50% Duty Cycle
MODE 10
V
CC
= Max.
PLL_EN = 1, LOCK = 1, MODE 10
REF_IN frequency = 50MHz.
All outputs open
—
62
3267 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
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