ispLSI3256E-70LB320 datasheet, PDF

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ispLSI3256E-70LB320: DescriptionIn-System Programmable High Density PLD; CategoryProgrammable logic devices Programmable logic; File Size157KB，15 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ispLSI3256E-70LB320 Overview

In-System Programmable High Density PLD

ispLSI3256E-70LB320 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA-320
Contacts	320
Reach Compliance Code	_compli
ECCN code	EAR99
Other features	SYNCHRONOUS & ASYNCHRONOUS CLOCKS; 32 GLBS
maximum clock frequency	70 MHz
In-system programmable	YES
JESD-30 code	S-PBGA-B320
JTAG BST	YES
length	40 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	256
Number of macro cells	256
Number of terminals	320
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 256 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA320,24X24,50
Package shape	SQUARE
Package form	GRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	4.5 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	40 mm
Base Number Matches	1

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ispLSI 3256E

In-System Programmable High Density PLD

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 256 I/O Pins

— 12000 PLD Gates

— 512 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E CMOS TECHNOLOGY

—

max

= 100 MHz Maximum Operating Frequency

—

= 10 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 5V In-System Programmable (ISP™) using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

ORP

D Q

ORP

Boundary

Scan

ORP

Array

D Q

ORP

AND Array

D Q

Twin

GLB

D Q

ORP

D Q

ORP

Global Routing Pool

ORP

0139A/3256E

Description

The ispLSI 3256E is a High Density Programmable Logic

Device containing 512 Registers, 256 Universal I/O pins,

five Dedicated Clock Input Pins, 16 Output Routing Pools

(ORP) and a Global Routing Pool (GRP) which allows

complete inter-connectivity between all of these ele-

ments. The ispLSI 3256E features 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3256E offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3256E device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256E

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

June 2002

3256e_08

ORP

Array

ORP

ispLSI3256E-70LB320 Related Products

	ispLSI3256E-70LB320	3256E	ispLSI3256E-100LQ
Description	In-System Programmable High Density PLD	In-System Programmable High Density PLD	In-System Programmable High Density PLD
Is it Rohs certified?	incompatible	-	incompatible
Parts packaging code	BGA	-	QFP
package instruction	BGA-320	-	PLASTIC, QFP-304
Contacts	320	-	304
Reach Compliance Code	_compli	-	_compli
ECCN code	EAR99	-	EAR99
Other features	SYNCHRONOUS & ASYNCHRONOUS CLOCKS; 32 GLBS	-	YES
maximum clock frequency	70 MHz	-	100 MHz
In-system programmable	YES	-	YES
JESD-30 code	S-PBGA-B320	-	S-PQFP-G304
JTAG BST	YES	-	YES
length	40 mm	-	40 mm
Humidity sensitivity level	3	-	3
Number of I/O lines	256	-	256
Number of macro cells	256	-	256
Number of terminals	320	-	304
Maximum operating temperature	70 °C	-	70 °C
organize	0 DEDICATED INPUTS, 256 I/O	-	0 DEDICATED INPUTS, 256 I/O
Output function	MACROCELL	-	MACROCELL
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	FBGA	-	FQFP
Encapsulate equivalent code	BGA320,24X24,50	-	QFP304,1.7SQ,20
Package shape	SQUARE	-	SQUARE
Package form	GRID ARRAY, FINE PITCH	-	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	225
power supply	5 V	-	5 V
Programmable logic type	EE PLD	-	EE PLD
propagation delay	15 ns	-	10 ns
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	4.5 mm	-	4.5 mm
Maximum supply voltage	5.25 V	-	5.25 V
Minimum supply voltage	4.75 V	-	4.75 V
Nominal supply voltage	5 V	-	5 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL
Terminal form	BALL	-	GULL WING
Terminal pitch	0.5 mm	-	0.5 mm
Terminal location	BOTTOM	-	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	30
width	40 mm	-	40 mm

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