3256E datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > 3256E

Preview

3256E: DescriptionIn-System Programmable High Density PLD; File Size157KB，15 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

Download Datasheet Compare View All

3256E Overview

In-System Programmable High Density PLD

Preview

Download Datasheet

View All

ispLSI 3256E

In-System Programmable High Density PLD

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 256 I/O Pins

— 12000 PLD Gates

— 512 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E CMOS TECHNOLOGY

—

max

= 100 MHz Maximum Operating Frequency

—

= 10 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 5V In-System Programmable (ISP™) using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

ORP

D Q

ORP

Boundary

Scan

ORP

Array

D Q

ORP

AND Array

D Q

Twin

GLB

D Q

ORP

D Q

ORP

Global Routing Pool

ORP

0139A/3256E

Description

The ispLSI 3256E is a High Density Programmable Logic

Device containing 512 Registers, 256 Universal I/O pins,

five Dedicated Clock Input Pins, 16 Output Routing Pools

(ORP) and a Global Routing Pool (GRP) which allows

complete inter-connectivity between all of these ele-

ments. The ispLSI 3256E features 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3256E offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3256E device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256E

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

June 2002

3256e_08

ORP

Array

ORP

3256E Related Products

	3256E	ispLSI3256E-100LQ	ispLSI3256E-70LB320
Description	In-System Programmable High Density PLD	In-System Programmable High Density PLD	In-System Programmable High Density PLD
Is it Rohs certified?	-	incompatible	incompatible
Parts packaging code	-	QFP	BGA
package instruction	-	PLASTIC, QFP-304	BGA-320
Contacts	-	304	320
Reach Compliance Code	-	_compli	_compli
ECCN code	-	EAR99	EAR99
Other features	-	YES	SYNCHRONOUS & ASYNCHRONOUS CLOCKS; 32 GLBS
maximum clock frequency	-	100 MHz	70 MHz
In-system programmable	-	YES	YES
JESD-30 code	-	S-PQFP-G304	S-PBGA-B320
JTAG BST	-	YES	YES
length	-	40 mm	40 mm
Humidity sensitivity level	-	3	3
Number of I/O lines	-	256	256
Number of macro cells	-	256	256
Number of terminals	-	304	320
Maximum operating temperature	-	70 °C	70 °C
organize	-	0 DEDICATED INPUTS, 256 I/O	0 DEDICATED INPUTS, 256 I/O
Output function	-	MACROCELL	MACROCELL
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	FQFP	FBGA
Encapsulate equivalent code	-	QFP304,1.7SQ,20	BGA320,24X24,50
Package shape	-	SQUARE	SQUARE
Package form	-	FLATPACK, FINE PITCH	GRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)	-	225	NOT SPECIFIED
power supply	-	5 V	5 V
Programmable logic type	-	EE PLD	EE PLD
propagation delay	-	10 ns	15 ns
Certification status	-	Not Qualified	Not Qualified
Maximum seat height	-	4.5 mm	4.5 mm
Maximum supply voltage	-	5.25 V	5.25 V
Minimum supply voltage	-	4.75 V	4.75 V
Nominal supply voltage	-	5 V	5 V
surface mount	-	YES	YES
technology	-	CMOS	CMOS
Temperature level	-	COMMERCIAL	COMMERCIAL
Terminal form	-	GULL WING	BALL
Terminal pitch	-	0.5 mm	0.5 mm
Terminal location	-	QUAD	BOTTOM
Maximum time at peak reflow temperature	-	30	NOT SPECIFIED
width	-	40 mm	40 mm

Recommended Resources

CD71061 Holiday Lights ASIC

RTS3350 circuit

Plot MAM-F (S) (A) circuit with current transformer

Switching regulated power supply composed of μA741

Circuit diagram of a diode connected in series across a potentiometer

555 simple car anti-traffic alarm circuit

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components