a
FEATURES
44 V Supply Maximum Rating
V
SS
to V
DD
Analog Signal Range
Single/Dual Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Microprocessor Compatible (100 ns
WR
Pulse)
Extended Plastic Temperature Range (–40 C to +85 C)
Low Leakage (20 pA Typ)
Low Power Dissipation (28 mW Max)
Available in DIP, SOIC, PLCC, and LCCC Packages
Superior Alternative to: DG526, DG527
CMOS Latched
8-/16-Channel Analog Multiplexers
ADG526A/ADG527A
FUNCTIONAL BLOCK DIAGRAM
ADG526A
S1
S1A
DA
S8A
D
S1B
DB
S16
DECODER/
LATCHES
S8B
DECODER/
LATCHES
ADG527A
WR
WR
A0 A1 A2 A3 EN
RS
A0 A1 A2 EN
RS
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels respectively.
On-chip latches facilitate microprocessor interfacing. The
ADG526A switches one of 16 inputs to a common output
depending on the state of four binary addresses and an enable
input. The ADG527A switches one of eight differential inputs
to a common differential output depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic compatible digital inputs.
The ADG526A and ADG527A are designed on an enhanced
LC
2
MOS process which gives an increased signal capability of
V
SS
to V
DD
and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single or dual supply range. These multiplex-
ers also feature high switching speeds and low R
ON
.
1. Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the 10.8 V to 16.5 V range for
both single and dual supplies.
2. Easily Interfaced: The ADG526A and ADG527A can be
easily interfaced with microprocessors. The
WR
signal latches
the state of the Address control lines and the Enable line.
The
RS
signal clears both the address and enable data in the
latches resulting in no output (all switches off).
RS
can be
tied to the microprocessor reset pin.
3. Extended Signal Range: The enhanced LC
2
MOS processing
results in a high breakdown and an increased analog signal
range of V
SS
to V
DD
.
4. Break-Before-Make Switching: Switches are guaranteed
break-before-make so that input signals are protected against
momentary shorting.
5. Low Leakage: Leakage currents in the range of 20 pA make
these multiplexers suitable for high precision circuits.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
Dual Supply
Parameter
ADG526A/ADG527A–SPECIFICATIONS
(V
DD
= +10.8 V to +16.5 V, V
SS
= –1O.8 V to –16.5 V unless otherwise noted.)
ADG526A/ADG527A
ADG526A
K Version
B Version
T Version
–40 C to
–40 C to
–55 C to
25 C +85 C
25°C +85 C
25 C +125 C Unit
V
SS
V
DD
280
450
300
R
ON
Drift
R
ON
Match
I
S
(OFF), Off Input Leakage
I
D
(OFF), Off Output Leakage
ADG526A
ADG527A
I
D
(ON), On Channel Leakage
ADG526A
ADG527A
I
DIFF
, Differential Off Output
Leakage (ADG527A Only)
0.6
5
0.02
1
0.04
1
1
0.04
1
1
V
SS
V
DD
V
SS
V
DD
280
450
300
0.6
5
0.02
1
0.04
1
1
0.04
1
1
V
SS
V
DD
V
SS
V
DD
280
450
300
0.6
5
0.02
1
0.04
1
0.04
1
V
SS
V
DD
V min
V max
Ω
typ
Ω
max
Ω
max
Ω
max
%/°C typ
% typ
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA max
2.4
0.8
1
8
200
300
50
25
200
300
200
300
100
V min
V max
µA
max
pF max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns min
ns min
ns min
ns min
dB typ
dB min
pF typ
pF typ
pF typ
pC typ
mA typ
mA max
µA
typ
mA max
mW typ
mW max
Comments
ANALOG
SWITCH
Analog Signal Range
R
ON
–10 V
≤
V
S
≤
+10 V, I
DS
= 1 mA;
Test Circuit 1
V
DD
= 15 V (± 10%), V
SS
= –15 V (± 10%)
V
DD
= 15 V (± 5%), V
SS
= –15 V (± 5%)
–10 V
≤
V
S
≤
+10 V, I
DS
= 1 mA
–10 V
≤
V
S
≤
+10 V, I
DS
= 1 mA
V1 =
±
10 V, V2 = 10 V; Test Circuit 2
V1 =
±
10 V, V2 =
V1 =
±
10 V, V2 =
10 V, Test Circuit 3
600
400
600
400
600
400
50
200
100
200
100
25
2.4
0.8
1
50
200
100
200
100
25
2.4
0.8
1
50
200
10 V; Test Circuit 4
200
V1 =
±
10 V, V2 =
10 V; Test Circuit 5
DIGITAL CONTROL
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INL
or I
INH
C
IN
Digital Input Capacitance
V
IN
= 0 to V
DD
8
8
200
300
50
25
200
300
200
300
100
DYNAMIC CHARACTERISTICS*
200
t
TRANSITION
300
50
t
OPEN
25
200
t
ON
(EN,
WR)
300
200
t
OFF
(EN,
RS)
300
100
t
W
Write Pulsewidth
t
S
Address Enable Setup Time
t
H
Address Enable Hold Time
t
RS
Reset Pulsewidth
OFF Isolation
68
50
5
44
22
4
0.6
V1 =
±
10 V, V2 =
Test Circuit 7
Test Circuit 8 and 9
10 V; Test Circuit 6
400
10
400
400
120
100
10
100
400
10
400
400
120
100
10
100
400
10
400
400
130
100
10
100
Test Circuit 8 and 10
See Figure 1
See Figure 1
See Figure 1
See Figure 2
V
EN
= 0.8 V, R
L
= 1 kΩ, C
L
= 15 pF,
V
S
= 7 V rms, f = 100 kHz
V
S
= 7 V rms, f = 100 kHz
V
EN
= 0.8 V
V
EN
= 0.8 V
R
S
= 0
Ω,
V
S
= 0 V; Test Circuit 11
V
IN
= V
INL
or V
INH
V
IN
= V
INL
or V
INH
68
50
5
44
22
4
0.6
1.5
20
0.2
10
28
68
50
5
44
4
0.6
1.5
20
0.2
10
28
C
S
(OFF)
C
D
(OFF)
ADG526A
ADG527A
Q
INJ
, Charge Injection
POWER SUPPLY
I
DD
I
SS
Power Dissipation
1.5
20
0.2
10
28
*Sample
tested at 25 C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
ADG526A/ADG527A
Single Supply
Parameter
ANALOG SWITCH
Analog Signal Range
R
ON
(V
DD
= 10.8 V to 16.5 V, V
SS
= GND to 0 V unless otherwise noted.)
ADG526A/ADG527A
ADG526A
K Version
B Version
T Version
–40 C to
–40 C to
–55 C to
25 C +85 C
25°C +85 C
25 C +125 C Unit
V
SS
V
DD
500
700
0.6
5
0.02
1
0.04
1
1
0.04
1
1
V
SS
V
DD
V
SS
V
DD
500
700
0.6
5
0.02
1
0.04
1
1
0.04
1
1
V
SS
V
DD
V
SS
V
DD
500
700
0.6
5
0.02
1
0.04
1
0.04
200
100
25
1
200
V
SS
V
DD
V min
V max
Ω
typ
Ω
max
%/°C typ
% typ
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA max
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 5
Comments
0 V
≤
V
S
≤
10 V, I
DS
= 0.5 mA;
Test Circuit 1
0 V
≤
V
S
≤
10 V, I
DS
= 0.5 mA
0 V
≤
V
S
≤
10 V, I
DS
= 0.5 mA
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 2
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 3
1000
1000
1000
R
ON
Drift
R
ON
Match
I
S
(OFF), Off Input Leakage
50
50
50
I
D
(OFF), Off Output Leakage
ADG526A
ADG527A
I
D
(ON), On Channel Leakage
ADG526A
ADG527A
I
DIFF
, Differential Off Output
Leakage (ADG527A only)
DIGITAL CONTROL
V
INH,
Input High Voltage
V
INL
, Input Low Voltage
I
INL
or I
INH
C
IN
Digital Input Capacitance
200
100
200
100
200
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 4
200
100
25
2.4
0.8
1
8
8
300
450
50
25
250
450
250
450
100
2.4
0.8
1
8
300
450
50
25
250
450
250
450
100
2.4
0.8
1
V min
V max
µA
max
pF max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns min
ns min
ns min
ns min
dB typ
dB min
pF typ
pF typ
pF typ
pC typ
mA typ
mA max
mW typ
mW max
V
IN
= 0 to V
DD
DYNAMIC CHARACTERISTICS*
300
t
TRANSITION
450
50
t
OPEN
25
250
t
ON
(EN,
WR)
450
250
t
OFF
(EN,
RS)
450
100
t
W
Write Pulsewidth
t
S
Address Enable Setup Time
t
H
Address Enable Hold Time
t
RS
Reset Pulsewidth
OFF Isolation
68
50
5
C
S
(OFF)
C
D
(OFF)
ADG526A
44
ADG527A
22
Q
INJ
, Charge Injection
4
POWER SUPPLY
I
DD
Power Dissipation
0.6
600
10
600
600
120
100
10
100
600
10
600
600
120
100
10
100
600
10
600
600
130
100
10
100
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 6
Test Circuit 7
Test Circuits 8 and 9
Test Circuits 8 and 10
See Figure 1
See Figure 1
See Figure 1
See Figure 2
V
EN
= 0.8 V, R
L
= 1 kΩ, C
L
= 15 pF
V
S
= 3.5 V rms, f = 100 kHz
V
EN
= 0.8 V
V
EN
= 0.8 V
R
S
= 0
Ω,
V
S
= 0 V; Test Circuit 11
V
IN
= V
INL
or V
INH
68
50
5
44
22
4
0.6
1.5
1.5
11
25
25
68
50
5
44
4
0.6
1.5
11
25
11
*Sample
tested at 25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
–3–
ADG526A/ADG527A
TIMING DIAGRAMS
3V
3V
WR
0V
1.5V
RS
0V
1.5V
t
W
t
S
3V
EN A0, A1, A2, (A3)
0V
2.0V
0.8V
t
RS
t
H
SWITCH
OUTPUT
t
OFF
(RS)
V
O
0V
0.8V
O
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level-sensitive; there-
fore, while
WR
is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of
WR.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C unless otherwise noted.)
Figure 2 shows the Reset Pulsewidth, t
RS
, and Reset Turn-off
Time, t
OFF
(RS).
Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V, t
R
= t
F
= 20 ns.
ORDERING GUIDE
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Analog Inputs
2
Voltage at S, D . . . . . . . . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V
. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA
Digital Inputs
2
Voltage at A, EN,
WR, RS
. . . . . . . . . V
SS
– 4 V to V
DD
+ 4 V
. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First
Power Dissipation (Any Package)
Up to 75°C by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2
Overvoltage at A, EN,
WR, RS,
S, or D will be clamped by diodes. Current should
be limited to the maximum rating above.
Model
1
ADG526AKN
ADG526AKR
ADG526AKP
ADG526ABQ
ADG526ATQ
3
ADG526ATE
3
ADG527AKN
ADG527AKR
ADG527AKP
ADG527ABQ
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Option
2
N-28
R-28
P-28A
Q-28
Q-28
E-28A
N-28
R-28
P-28A
Q-28
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
See Analog Devices Military Products Databook (1990) for military data.
2
E = Leadless Ceramic Chip Carrier; N = Narrow Plastic DIP; P = Plastic
Leaded Chip Carrier; Q = CERDIP; R = 0.3" Small Outline IC (SOIC).
3
Standard Military Drawing (SMD) assigned by DESC. SMD numbers are:
5962-89710013X (ADG526ATE/883B)
5962-8971001XX (ADG526ATQ/883B)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG526A/ADG527A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
ADG526A/ADG527A
TRUTH TABLES
ADG526A
A3
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Al
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
X
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
WR
g
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RS
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ON SWITCH
Retains Previous Switch Condition
NONE (Address and Enable Latches Cleared)
NONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X = Don’t Care
ADG527A
A2
X
X
X
0
0
0
0
1
1
1
1
Al
X
X
X
0
0
1
1
0
0
1
1
A0
X
X
X
0
1
0
1
0
1
0
1
EN
X
X
0
1
1
1
1
1
1
1
1
WR
g
X
0
0
0
0
0
0
0
0
0
RS
1
0
1
1
1
1
1
1
1
1
1
ON SWITCH PAIR
Retains Previous Switch Condition
NONE (Address and Enable Latches Cleared)
NONE
1
2
3
4
5
6
7
8
X = Don’t Care
REV. B
–5–
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