PPC405EX-SSA666T datasheet, PDF

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PPC405EX-SSA666T: DescriptionRISC Microprocessor, 32-Bit, 667MHz, CMOS, PBGA388, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, MS-034C, EBGA-388; CategoryThe embedded processor and controller Microcontrollers and processors; File Size988KB，67 Pages; ManufacturerApplied Micro Circuits (MACOM); Environmental Compliance

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PPC405EX-SSA666T Overview

RISC Microprocessor, 32-Bit, 667MHz, CMOS, PBGA388, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, MS-034C, EBGA-388

PPC405EX-SSA666T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Applied Micro Circuits (MACOM)
Parts packaging code	BGA
package instruction	BGA,
Contacts	388
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width
bit size	32
boundary scan	YES
maximum clock frequency	666.66 MHz
External data bus width
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B388
length	27 mm
low power mode	YES
Number of terminals	388
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	2.65 mm
speed	667 MHz
Maximum supply voltage	1.3 V
Minimum supply voltage	1.1 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	27 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Part Number 405EX

Revision 1.09 - August 21, 2007

405EX

PowerPC 405EX Embedded Processor

Features

• AMCC PowerPC

405 32-bit RISC processor core

operating from 333MHz to 667MHz including

16KB I- and D-caches with parity checking

• On-chip 128-bit processor local bus (PLB)

operating up to 200MHz

• On-chip 32-bit peripheral bus (OPB) operating up

to 100 MHz

• External 8-,16-, or 32-bit peripheral bus (EBC)

operating up to 100MHz

• External bus master (EBM) operating up to

100MHz

• On-chip Security feature with True Random

Number generation

• Eight- and 16-bit NAND Flash interface

• Inter-chip connectivity (SCP and IIC)

• Boot from NOR Flash on the external peripheral

bus or NAND Flash on the NAND Flash interface

• DMA (4-channel) support for all on-chip slaves

and external bus, UARTs, and devices on the EBC

• DDR1/2 SDRAM interface operating up to 400

Mbps

Preliminary Data Sheet

• Two one-lane PCI Express interfaces operating up

to 2.5 Gbps

• Two Gigabit Ethernet interfaces (half- and full-

duplex) to external PHY (GMII/RGMII)

• USB 2.0 OTG port configurable as either Host or

Device

• Programmable universal interrupt controller (UIC)

• General Purpose Timer (GPT)

• Up to two serial ports (16750 compatible UART)

• Two IIC interfaces operating up to 400kHz and

supporting all standard IIC EEPROMs

• One SCP (SPI) synchronous full-duplex channel

operating up to 25 MHz

• General purpose I/Os (GPIOs), each with

programmable interrupts and outputs

• Supports JTAG for board-level testing

• System power management, low power

dissipation and small form factor

• Available in a RoHS compliant (lead-free) package

Description

With speeds up to 667MHz, a flexible off-chip memory

architecture, and a diverse communications package

that includes PCI Express, USB 2.0 OTG, and

10/100/1000 Ethernet, the PowerPC 405EX

embedded processor provides a low power and small

footprint system-on-a-chip (SOC) solution for a wide

range of high performance, cost-constrained

embedded applications. This includes wireless LAN

applications, security appliances, internet appliances,

line cards, and intelligent USB peripherals. It is an

easily programmable general purpose, 32-bit RISC

controller that offers an upgrade path for applications

in need of performance and connectivity

improvements.

Technology: Cu-08 CMOS, 90nm

Package: 388-ball, 27mm

27mm, enhanced plastic

ball grid array (EPBGA), 1mm ball pitch

Power consumption (est.): less than 2W, typical

Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM

only), and 1.2V

AMCC Proprietary

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

Preliminary Data Sheet

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Power PC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Security Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Serial Communication Port Interface (SCP/SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

General Purpose I/O (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Signal Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Ratings and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

DDR 1/2 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

AMCC Proprietary

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

Preliminary Data Sheet

List of Figures

Figure 1. PPC405EX Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Package 27mm, 388-Ball EPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 4. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 5. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 6. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 7. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 8. DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 9. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 10. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

List of Tables

Table 1. System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 5. Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 10. I/O Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 11. Typical DC Power Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 13. DC Power Supply Loads with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 14. DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 15. System Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 16. Peripheral Interface I/O Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 17. I/O Specifications—All CPU Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 18. I/O Specifications—333 MHz to 667 MHz CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 19. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 20. DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 21. I/O Timing—DDR SDRAM T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 22. I/O Timing—DDR SDRAM T

, T

, and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 23. I/O Timing—DDR SDRAM Write TimingT

and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 24. I/O Timing—DDR SDRAM Read Timing T

and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 25. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

AMCC Proprietary

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