8A34012B-000NLG8 datasheet, PDF

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8A34012B-000NLG8: DescriptionVFQFPN-72, Reel; CategoryWireless rf/communication Telecom circuit; File Size2MB，104 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8A34012B-000NLG8 Overview

VFQFPN-72, Reel

8A34012B-000NLG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	,
Contacts	72
Manufacturer packaging code	NLG72P4
Reach Compliance Code	compliant
Telecom integrated circuit types	TELECOM CIRCUIT
Base Number Matches	1

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Port Synchronizer for IEEE 1588

Frequency and Time/Phase

Datasheet

8A34012

Overview

The 8A34012 is a port synchronizer for frequency and time/phase

for equipment that uses packet-based and physical layer-based

equipment synchronization.

The 8A34012 is a highly integrated device that provides tools to

manage timing references, clock sources, and timing paths for

IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The

PLL channels can act independently as frequency synthesizers,

jitter attenuators, Digitally Controlled Oscillators (DCO) or Digital

Phase Lock Loops (DPLL).

▪

differential /

single-ended clock inputs

•

Per-input programmable phase offset of up to ±1.638s in

1ps steps

LOS, activity, frequency monitoring and/or LOS input pins

to any input clock reference

Support frequencies from 1kHz to 1GHz

Any input can be mapped to any or all of the timing channels

Redundant inputs frequency independent of each other

Any input can be designated as external frame/sync pulse of

EPPS (even pulse per second), 1 PPS (Pulse per Second),

5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz

associated with a selectable reference clock input

Typical Applications

▪

Core and access IP switches / routers

▪

Synchronous Ethernet equipment

▪

Telecom Boundary Clocks (T-BCs) and Telecom Time Slave

Clocks (T-TSCs) according to ITU-T G.8273.2

▪

Reference monitors qualify/disqualify references depending on

•

Loss of Signal (LOS) input pins (via GPIOs) can be assigned

▪

Automatic reference selection state machines select the active

reference for each DPLL based on the reference monitors,

priority tables, revertive / non-revertive, and other

programmable settings

to 54MHz or from a crystal oscillator

▪

10Gb, 40Gb and 100Gb Ethernet interfaces

▪

Central Office Timing Source and Distribution

▪

Wireless infrastructure for 4.5G and 5G network equipment

▪

System APLL operates from fundamental-mode crystal: 25MHz

▪

System DPLL accepts an XO, TCXO, or OCXO operating at

virtually any frequency from 1MHz to 150MHz

Time Protocol (PTP) / IEEE 1588 clocks

less than 1.11 × 10

-16

Features

▪

Four independent timing channels

▪

DPLLs can be configured as DCOs to synthesize Precision

•

Each can act as a frequency synthesizer, jitter attenuator,

•

DPLL Digital Loop Filters (DLFs) are programmable with

•

Switching between DPLL and DCO modes is hitless and

cut-off frequencies from 17Hz to 22kHz

dynamic

Digitally Controlled Oscillator (DCO), or Digital Phase Lock

Loop (DPLL)

•

DCOs generate PTP based clocks with frequency resolution

▪

DPLL Phase detectors can be used as Time-to-Digital

▪

Supports 1MHz I

C or 50MHz SPI serial processor ports

▪

Can configure itself automatically after reset via:

Converters (TDC) with precision below 1ps

•

Generates output frequencies that are independent of input

▪

8 Differential / 16 LVCMOS outputs

•

Internal customer definable One-Time Programmable

memory with up to 16 different configurations

•

Each FOD supports output phase tuning with 1ps resolution

•

Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)

•

Jitter below 150fs RMS (10kHz to 20MHz)

•

LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL

•

Differential output swing is selectable: 400mV / 650mV /

•

Independent output voltages of 3.3V, 2.5V, or 1.8V

•

The clock phase of each output is individually programmable

in 1ns to 2ns steps with a total range of ±180°

800mV / 910mV

output modes supported

frequencies via a Fractional Output Divider (FOD)

▪

1149.1 JTAG Boundary Scan

▪

10 × 10 mm, 72-QFN package

•

Standard external I

C EPROM via separate I

C Master Port

▪

LVCMOS additionally supports 1.5V or 1.2V

September 8, 2020

8A34012 Datasheet

The System DPLL generates an internal system clock that is used by the reference monitors and other digital circuitry in the device. If the

reference provided to the System APLL meets the stability and accuracy requirements of the intended application then the System DPLL

can free run and a System DPLL reference is not required. Alternatively, the System DPLL can be locked to an external reference that

meets the stability and accuracy requirements of the intended application. The System DPLL can accept an external reference from the

XO_DPLL pin or via the reference selection mux.

The frequency accuracy/stability of the internal system clock determines the frequency accuracy/stability of the DPLLs in Free-Run mode

and in Holdover mode; and it affects the wander generation of the DPLLs in Locked and DCO modes. When provided with a suitably

stable and accurate system clock, the DPLLs meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise tolerance,

transient response, and holdover performance requirements of ITU-T G.8262 synchronous Ethernet Equipment Clock (EEC) options 1

and 2.

The 8A34012 accepts up to seven differential reference inputs and up to 14 single-ended reference inputs that can operate at common

GNSS, Ethernet, SONET/SDH, PDH frequencies, and any input frequency from 1kHz to 1GHz (250MHz in single-ended mode). The

references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references are

available to all the DPLLs. The active reference for each DPLL is determined by forced selection or by automatic selection based on user

programmed priorities, locking allowances, reference monitors, revertive and non-revertive settings, and LOS inputs.

The 8A34012 can accept a clock reference and an associated frame pulse or sync signal as a pair. DPLLs can lock to the clock reference

and align the sync and clock outputs with the paired sync/frame input. The device allows any of the reference inputs to be configured as

sync inputs that can be associated with any of the other reference inputs. The input sync signals can have a frequency of 1 PPS (Pulse

per Second), EPPS (even pulse per second), 5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8 kHz. This feature enables the

DPLLs to phase align its frame sync and clock outputs with a sync input without the need to use a low bandwidth setting to lock directly to

the sync input.

The DPLLs support four primary operating modes: Free-Run, Locked, Holdover, and DCO. In Free-Run mode the DPLLs synthesize

clocks based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. Also in

Locked mode, the long-term output frequency accuracy is the same as the long term frequency accuracy of the selected input reference.

In Holdover mode, the DPLL uses frequency data acquired while in Locked mode to generate accurate frequencies when input

references are not available. In DCO mode, the DPLL control loop is opened and the DCO can be controlled by a PTP clock recovery

servo running on an external processor to synthesize PTP clocks.

The DPLLs can be configured with a range of selectable filtering bandwidths from 17Hz to 22kHz for use in jitter attenuation and rate

conversion applications.

The 8A34012 generates up to eight differential output clocks at any frequency from 0.5Hz to 1GHz. The differential outputs can support

LVPECL, LVDS, HCSL, and CML. It generates up to 16 single-ended clocks with frequencies from 0.5Hz to 250MHz. LVCMOS output

supports 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V. Each output stage can be independently configured.

Clocks generated by the 8A34012 have jitter below 150fs RMS (10kHz to 20MHz) and therefore are suitable for serial 100GBASE-R,

40GBASE-R, and lower rate interfaces.

All control and status registers are accessed through the I

C /SPI slave microprocessor interface, the SPI interface mode supports high

clock rates (up to 50MHz). For configuring the DPLLs, the I

C master interface can automatically load a configuration from an external

EEPROM after reset. The 8A34012 also has internal customer definable One-Time Programmable memory with up to 16 different

configurations.

September 8, 2020

8A34012 Datasheet

Contents

Overview .............................................................................................................................................................................................................. 1

Typical Applications.............................................................................................................................................................................................. 1

Features ............................................................................................................................................................................................................... 1

Block Diagram ...................................................................................................................................................................................................... 2

Description ............................................................................................................................................................................................................ 2

Pin Assignment .................................................................................................................................................................................................. 10

Pin Description and Pin Characteristic Tables .................................................................................................................................................. 11

Overview of the 8A3xxxx Family ........................................................................................................................................................................ 16

Functional Description........................................................................................................................................................................................ 16

Basic Functional Blocks ..................................................................................................................................................................................... 17

Crystal Input (OSCI / OSCO) ...................................................................................................................................................................... 17

Frequency Representation ................................................................................................................................................................ 17

System APLL .............................................................................................................................................................................................. 17

Input Stage.................................................................................................................................................................................................. 18

Reference Monitoring.................................................................................................................................................................................. 21

Loss of Signal (LOS) Monitoring........................................................................................................................................................ 21

Activity ............................................................................................................................................................................................... 22

Timer ................................................................................................................................................................................................. 22

Frequency Offset Monitoring ............................................................................................................................................................. 23

Advanced Input Clock Qualification ............................................................................................................................................................ 23

Input Clock Qualification.................................................................................................................................................................... 23

Clock Reference Disqualifier through GPIO...................................................................................................................................... 24

Frame Pulse Operation............................................................................................................................................................................... 24

Sync Pulse Operation ................................................................................................................................................................................. 25

Crystal Oscillator Input (XO_DPLL) ............................................................................................................................................................ 26

Digital Phase Locked Loop (DPLL) ............................................................................................................................................................. 26

Free-Run Mode ................................................................................................................................................................................. 28

Locked Mode..................................................................................................................................................................................... 28

Holdover Mode .................................................................................................................................................................................. 28

Manual Holdover Mode ..................................................................................................................................................................... 28

External Feedback............................................................................................................................................................................. 29

DPLL Input Clock Qualification and Selection............................................................................................................................................. 29

Automatic Input Clock Selection........................................................................................................................................................ 30

Manual Input Clock Selection via Register or GPIO.......................................................................................................................... 30

Slave or GPIO Slave Selection.......................................................................................................................................................... 30

DPLL Switchover Management................................................................................................................................................................... 30

Revertive and Non-Revertive Switching ............................................................................................................................................ 30

Hitless Reference Switching.............................................................................................................................................................. 30

Phase Slope Limiting......................................................................................................................................................................... 31

DPLL Frequency Offset Limit Setting ................................................................................................................................................ 31

DPLL Fast Lock Operation.......................................................................................................................................................................... 32

Steerable Fractional Output Divider (FOD)................................................................................................................................................. 32

FOD Multiplexing and Output Stages.......................................................................................................................................................... 33

Integer Output Divider ....................................................................................................................................................................... 34

Output Duty Cycle Adjustment .......................................................................................................................................................... 35

Output Coarse Phase Adjustment ..................................................................................................................................................... 35

Output Buffer ..................................................................................................................................................................................... 36

September 8, 2020

8A34012 Datasheet

General Purpose Input/Outputs (GPIOs) .................................................................................................................................................... 37

GPIO Modes...................................................................................................................................................................................... 37

GPIO Pin Configuration..................................................................................................................................................................... 38

Alarm Output Operation..................................................................................................................................................................... 39

Device Initial Configuration ......................................................................................................................................................................... 40

Use of GPIO Pins at Reset................................................................................................................................................................ 40

Default Values for Registers.............................................................................................................................................................. 41

One-Time Programmable (OTP) Memory................................................................................................................................................... 41

Configuration Data in OTP ................................................................................................................................................................ 42

Use of External I

C EEPROM..................................................................................................................................................................... 42

Device Updates in External I

C EEPROM ........................................................................................................................................ 42

Configuration Data in External I2C EEPROM ................................................................................................................................... 42

Reset Sequence.......................................................................................................................................................................................... 43

Step 0 – Reset Sequence Starting Condition.................................................................................................................................... 43

Step 1 – Negation of nMR (Rising Edge) .......................................................................................................................................... 43

Step 2 – Internally Set Default Conditions......................................................................................................................................... 43

Step 3 – Scan for Device Updates in EEPROM................................................................................................................................ 44

Step 4 – Read Configuration from OTP............................................................................................................................................. 44

Step 5 – Search for Configuration in External EEPROM................................................................................................................... 44

Step 6 - Load OTP Hotfix and Execute ............................................................................................................................................. 45

Step 7 – Complete Configuration ...................................................................................................................................................... 45

Clock Gating and Logic Power-Down Control............................................................................................................................................. 45

Serial Port Functions................................................................................................................................................................................... 45

Addressing Registers within the 8A34012......................................................................................................................................... 46

I2C Slave Operation .......................................................................................................................................................................... 47

I2C Master ......................................................................................................................................................................................... 49

SPI Operation .................................................................................................................................................................................... 50

JTAG Interface ............................................................................................................................................................................................ 53

Basic Operating Modes (Synthesizer / Clock Generator / Jitter Attenuator) ...................................................................................................... 54

Free-Running Synthesizer Operation.......................................................................................................................................................... 54

Clock Generator Operation ......................................................................................................................................................................... 54

Synthesizer Disciplined with Oscillator Operation....................................................................................................................................... 55

Jitter Attenuator Operation.......................................................................................................................................................................... 55

Jitter Attenuator Operation with External Digital Loop Filter ....................................................................................................................... 56

Jitter Attenuator Disciplined with Oscillator Operation ................................................................................................................................ 56

Digitally-Controlled Oscillator Operation via External Control..................................................................................................................... 57

Write-Frequency Mode...................................................................................................................................................................... 57

Increment / Decrement Registers and Pins....................................................................................................................................... 58

Write-Phase Mode............................................................................................................................................................................. 58

Adjusting Phase while in Closed Loop Operation ....................................................................................................................................... 59

Combo Mode............................................................................................................................................................................................... 59

Satellite Channel......................................................................................................................................................................................... 60

Time-of-Day (ToD) Operation ..................................................................................................................................................................... 62

ToD Triggers and Latches................................................................................................................................................................. 62

GPIO Functions Associated with ToD Operation .............................................................................................................................. 64

Pulse-Width Modulation Encoders, Decoders, and FIFO ........................................................................................................................... 64

PWM Signature ................................................................................................................................................................................. 65

PWM Frames..................................................................................................................................................................................... 65

1PPS and ToD Distribution (PWM_PPS) .......................................................................................................................................... 66

September 8, 2020

8A34012B-000NLG8 Related Products

	8A34012B-000NLG8	8A34012B-000NLG	8A34012B-000NLG#
Description	VFQFPN-72, Reel	VFQFPN-72, Tray	VFQFPN-72, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN	VFQFPN	VFQFPN
Contacts	72	72	72
Manufacturer packaging code	NLG72P4	NLG72P4	NLG72P4
Reach Compliance Code	compliant	compliant	compliant
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Base Number Matches	1	1	1

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