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8400002EA

Description
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125
Categorylogic    logic   
File Size1022KB,16 Pages
ManufacturerTexas Instruments
Websitehttp://www.ti.com.cn/
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8400002EA Overview

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125

8400002EA Parametric

Parameter NameAttribute value
Brand NameTexas Instruments
MakerTexas Instruments
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codenot_compliant
Factory Lead Time1 week
seriesALS
JESD-30 codeR-GDIP-T16
JESD-609 codee0
length19.56 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-K FLIP-FLOP
Maximum Frequency@Nom-Sup25000000 Hz
MaximumI(ol)-0.0004 A
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
method of packingTUBE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)4 mA
Prop。Delay @ Nom-Sup18 ns
propagation delay (tpd)24 ns
Certification statusQualified
Schmitt triggerNo
Filter levelMIL-STD-883
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeNEGATIVE EDGE
width6.92 mm
minfmax25 MHz
Base Number Matches1
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