low-cost, nonvolatile, read/write storage solution for
a wide range of applications. The LH28F160SGED-
L10 is the highest density, highest performance
non-volatile read/write solution for solid-state
storage applications. LH28F160SGED-L10 can
read/write/erase at V
CC
= 2.7 V and V
PP
= 2.7 V.
Its low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Its symmetrically-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for resident flash
arrays, SIMMs and memory cards. Its enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F160SGED-L10
offers three levels of protection : absolute protection
with V
PP
at GND, selective hardware block locking,
or flexible software block locking. These alternatives
give designers ultimate control of their code security
needs.
16 M-bit (512 kB x 16 x 2-Bank)
SmartVoltage Dual Work Flash Memory
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with V
PP
= GND
– Flexible block locking
– Block erase/word write lockout during power
transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
– Thirty-two 32 k-word erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/bank
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases Icc
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOX
TM
∗
V nonvolatile flash technology
• Package
– 48-pin TSOP Type I (TSOP048-P-1220)
Normal bend
∗
ETOX is a trademark of Intel Corporation.
FEATURES
• SmartVoltage Dual Work technology
– 2.7 V, 3.3 V or 5 V V
CC
– 2.7 V, 3.3 V, 5 V or 12 V V
PP
– Capable of performing erase, write and read
for each bank independently (Impossible to
perform read from both banks at a time).
• High performance read access time
– 100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/
120 ns (2.7 to 3.6 V)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F160SGED-L10
PIN CONNECTIONS
48-PIN TSOP (Type I)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
NC
WE#
RP#
V
PP
WP#
NC
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TOP VIEW
A
16
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE#
GND
BE
1
#
BE
0
#
A
0
(TSOP048-P-1220)
-2-
LH28F160SGED-L10
BLOCK DIAGRAM
Bank1
Bank0
DQ
0
-DQ
15
OUTPUT
BUFFER
INPUT
BUFFER
BE
1
#
I/O
LOGIC
DATA
REGISTER
OUTPUT
MULTIPLEXER
IDENTIFIER
REGISTER
V
CC
BE
0
#
STATUS
REGISTER
COMMAND
USER
INTERFACE
WE#
OE#
WP#
RP#
DATA
COMPARATOR
A
0
-A
18
INPUT
BUFFER
Y DECODER
Y GATING
WRITE
STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
V
PP
ADDRESS
LATCH
X DECODER
16
32 k-WORD
BLOCKS
V
CC
GND
ADDRESS
COUNTER
-3-
LH28F160SGED-L10
PIN DESCRIPTION
SYMBOL
A
0
-A
18
TYPE
INPUT
NAME AND FUNCTION
ADDRESS INPUTS :
Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS :
Inputs data and commands during CUI write cycles; outputs
DQ
0
-DQ
15
INPUT/
OUTPUT
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
BANK ENABLE :
Activates the device’s control logic, input buffers, decoders, and
BE
0
#,
BE
1
#
INPUT
sense amplifiers. When BE
0
# are "low", bank0 is in active. When BE
1
# are "low", bank1
is in active. Both BE
0
# and BE
1
# must not be low at the same time. BE
0
#, BE
1
#-high
deselects the device and reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN :
Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
RP#
INPUT
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
RP# at V
HH
allows to set permanent lock-bit. Block erase, word write, or lock-bit
configuration with V
IH
≤
RP#
≤
V
HH
produce spurious results and should not be
attempted.
OE#
WE#
WP#
INPUT
INPUT
INPUT
OUTPUT ENABLE :
Controls the device's outputs during a read cycle.
WRITE ENABLE :
Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT :
Master control for block locking. When V
IL
, locked blocks cannot be
erased and programmed, and block lock-bits cannot be set and reset.
BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
For erasing array blocks, writing words, or configuring lock-bits. With V
PP
≤
V
PPLK
,
V
PP
SUPPLY
memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid V
PP
(see
Section 6.2.3 "DC CHARACTERISTICS")
produce spurious
results and should not be attempted.
DEVICE POWER SUPPLY :
Internal detection configured the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp V
CC
down to GND and then
V
CC
SUPPLY
ramp V
CC
to the new voltage. Do not float any power pins. With V
CC
≤
V
LKO
, all write
attempts to the flash memory are inhibited. Device operations at invalid V
CC
voltage
(see
Section 6.2.3 "DC CHARACTERISTICS")
produce spurious results and should
GND
NC
SUPPLY
not be attempted.
GROUND :
Do not float any ground pins.
NO CONNECT :
Lead is not internal connected; recommend to be floated.
-4-
LH28F160SGED-L10
1 INTRODUCTION
This datasheet contains LH28F160SGED-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160SGED-
L10 flash memory documentation also includes
ordering information which is referenced in
Section 7.
select one of banks. BE
0
# is assigned to No. 26
pin which is CE# in LH28F800SGE-L10, BE
1
#
is assigned to No. 27 pin which is GND in
LH28F800SGE-L10. To select either bank (bank0)
BE
0
# must be "L", and to select another bank
(bank1) BE
1
# must be "L". Selecting both banks
(bank0 and bank1) at a time, except of read
operation (array read, status register read), turns
both BE
0
# and BE
1
# to "L".
Operation mode of bank0 and bank1 as follows :
1) Both bank0 and bank1 are in deep power-down
(RP# = "L").
2) Both bank0 and bank1 are in standby
(BE
0
# = BE
1
# = "H").
3) Bank0 is in standby and bank1 is in active state
of programming or erase, or bank0 is in active
state of programming or erase and bank1 is in
standby.
4) Both bank0 and bank1 are in active state
(impossible to perform simultaneous read from
both banks). In this case bank0 and bank1
perform independent operation, for example,
after input Erase command to bank0 erase or
program command to bank1 is succeeded,
bank0 and bank1 perform each operation
concurrently.
SmartVoltage technology provides a choice of V
CC
and V
PP
combinations, as shown in
Table 1,
to
meet system performance and power expectations.
2.7 to 3.6 V V
CC
consumes approximately one-fifth
the power of 5 V V
CC
. But, 5 V V
CC
provides the
highest read performance. V
PP
at 3.3 V and 5 V
eliminates the need for a separate 12 V converter,
while V
PP
= 12 V maximizes block erase and word
write performance. In addition to flexible erase and
program voltages, the dedicated V
PP
pin gives
complete data protection when V
PP
≤
V
PPLK
.
1.1
New Features
Key enhancements of LH28F160SGED-L10
SmartVoltage Dual Work flash memory are :
• SmartVoltage Dual Work Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
• Permanent Lock Capability
Note following important differences :
• V
PPLK
has been lowered to 1.5 V to support
3.3 V and 5 V block erase, word write, and lock-
bit configuration operations. Designs that switch
V
PP
off during read operations should make sure
that the V
PP
voltage transitions to GND.
• To take advantage of SmartVoltage technology,
allow V
CC
connection to 2.7 V, 3.3 V or 5 V.
• Once set the permanent lock bit, the blocks
which have been set block lock-bit can not be
erased, written forever.
1.2
Product Overview
The LH28F160SGED-L10 is a high-performance
16 M-bit SmartVoltage Dual Work flash memory
organized as 1 024 k-word of 16 bits. The 1 024 k-
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