Data Sheet
November 2001
LCK4950
Low-Voltage PLL Clock Driver
Features
s
s
s
s
s
Fully integrated phase-locked loop (PLL)
Oscillator or crystal reference input
Output frequency up to 180 MHz
Outputs disable in high impedance
Compatible with
PowerPC
®
,
Intel
®
, and high-
performance RISC microprocessors
TQFP packaging
Output frequency configurable
±35 ps typical cycle-to-cycle jitter
Pin compatible with the
Motorola
®
MPC950 clock
driver
To provide input reference clock flexibility, two
selectable division ratios are available on the
LCK4950. The internal V
CO
runs at either 2x or 4x
the high-speed output. The FBSEL pin is used to
select between a divide by 8 or a divide by 16 of the
V
CO
frequency to be compared with the input
reference. These selections allow the input reference
to be either one-half, one-fourth, or one-eighth of the
high-speed output.
The LCK4950 is capable of scan clock distribution or
system diagnostics due to an external test clock
input. The REF_SEL pin allows the selection
between a crystal input to an on-chip oscillator for the
reference or selection of a TTL level oscillator input
directly. Only a parallel resonant crystal is required
for the onboard crystal oscillator external
components.
The LCK4950 is fully 3.3 V compatible and requires
no external loop filter components. All inputs accept
LVCMOS or LVTTL compatible levels while the
outputs provide LVCMOS levels with the capability to
drive terminated 50
Ω
transmission lines. The
LCK4950 can drive two traces, giving the device an
effective fan out of 1:18 for series-terminated 50
Ω
lines. For optimum performance and board density,
the device is packaged in a 7 mm x 7 mm 32-lead
TQFP package.
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Description
The LCK4950 is a PLL-based clock driver device
intended for high-performance clock tree designs.
The LCK4950 is 3.3 V compatible with output
frequencies of up to 180 MHz and output skews of
200 ps. The LCK4950 can accommodate the most
demanding tree designs by employing a fully
differential PLL design. This minimizes cycle-to-cycle
jitter, which is critical when the device is acting as the
reference clock for PLLs in today’s microprocessors
and ASICs. The device has nine low-skew
configurable outputs for support of the clocking
needs of the various high-performance
microprocessors.
LCK4950
Low-Voltage PLL Clock Driver
Data Sheet
November 2001
Functional Description
(continued)
Table 2. Function Table
Inputs
fsela
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
fselb
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
fselc
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
fseld
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Qa(1)
2x
2x
2x
2x
2x
2x
2x
2x
x
x
x
x
x
x
x
x
Outputs
Qb(1)
x
x
x
x
x/2
x/2
x/2
x/2
x
x
x
x
x/2
x/2
x/2
x/2
Qc(2)
x
x
x/2
x/2
x
x
x/2
x/2
x
x
x/2
x/2
x
x
x/2
x/2
Qd(5)
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
Total 2x
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Totals
Total x
8
3
6
1
7
2
3
0
9
4
7
2
8
3
6
1
Total x/2
0
5
2
7
1
6
5
8
0
5
2
7
1
6
3
8
Note: x = fVCO/4; 200 MHz < fVCO < 480 MHz.
Table 3. PLL Input Reference Characteristics
Characteristic
TCLK Input Rise/Falls
Reference Input Frequency
Crystal Oscillator Frequency
†
Reference Input Duty Cycle
Symbol
t
r
, t
f
f
ref
f
Xtal
f
refdc
Min
—
—*
12.5
25
Max
3.0
—*
25
75
Unit
ns
MHz
MHz
%
* Maximum and minimum input reference is limited by the V
CO
lock range and the feedback divider for the TCLK or xtal1 inputs.
† See the Applications section for more crystal information.
4
Agere Systems Inc.
Data Sheet
November 2001
LCK4950
Low-Voltage PLL Clock Driver
Applications
Programming the LCK4950S
Several frequency relationships are configurable by the LCK4950. Frequency ratios of 1:1, 2:1, 4:1, and 4:2:1 are
possible from configuring the output dividers for the four output groups. To ensure that the output duty cycle is
always 50%, the LCK4950 uses even dividers. Table 4 illustrates output configurations of the LCK4950, describing
the outputs using the V
CO
frequency as a reference. For example, setting the Qa outputs to V
CO
/2, the Qb and Qc
to V
CO
/4, and the Qd to V
CO
/8 would provide the output frequency relationship of 4:2:1.
Table 4. Programmable Output Frequency Relationships
Inputs
FSELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FSELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Qa
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
Qb
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/8
V
CO
/8
Outputs
Qc
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
Qd
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
The division settings establish the output relationship, but one must still ensure that the V
CO
will be stable given the
frequency of the outputs desired. The feedback frequency should be used to situate the V
CO
into a frequency
range in which the PLL will be stable. The design of the PLL is such that for output frequencies between 25 MHz
and 180 MHz, the LCK4950 can generally be configured into a stable region.
Agere Systems Inc.
5
Embedded System
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